JPS51116677A - Adhesion structure - Google Patents

Adhesion structure

Info

Publication number
JPS51116677A
JPS51116677A JP50041336A JP4133675A JPS51116677A JP S51116677 A JPS51116677 A JP S51116677A JP 50041336 A JP50041336 A JP 50041336A JP 4133675 A JP4133675 A JP 4133675A JP S51116677 A JPS51116677 A JP S51116677A
Authority
JP
Japan
Prior art keywords
adhesion structure
dimensionally
adhesion
lead wires
reduce spacing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP50041336A
Other languages
Japanese (ja)
Inventor
Isao Yoshida
Toshiaki Masuhara
Hiroo Masuda
Jun Eto
Ryoichi Hori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP50041336A priority Critical patent/JPS51116677A/en
Publication of JPS51116677A publication Critical patent/JPS51116677A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/654—Top-view layouts
    • H10W70/655—Fan-out layouts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE: To reduce spacing by arranging lead wires three-dimensionally.
COPYRIGHT: (C)1976,JPO&Japio
JP50041336A 1975-04-07 1975-04-07 Adhesion structure Pending JPS51116677A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50041336A JPS51116677A (en) 1975-04-07 1975-04-07 Adhesion structure

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50041336A JPS51116677A (en) 1975-04-07 1975-04-07 Adhesion structure

Publications (1)

Publication Number Publication Date
JPS51116677A true JPS51116677A (en) 1976-10-14

Family

ID=12605666

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50041336A Pending JPS51116677A (en) 1975-04-07 1975-04-07 Adhesion structure

Country Status (1)

Country Link
JP (1) JPS51116677A (en)

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