JPS51117860A - Phase lock loop - Google Patents

Phase lock loop

Info

Publication number
JPS51117860A
JPS51117860A JP50042371A JP4237175A JPS51117860A JP S51117860 A JPS51117860 A JP S51117860A JP 50042371 A JP50042371 A JP 50042371A JP 4237175 A JP4237175 A JP 4237175A JP S51117860 A JPS51117860 A JP S51117860A
Authority
JP
Japan
Prior art keywords
phase lock
lock loop
jitter
small amount
pll circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP50042371A
Other languages
Japanese (ja)
Inventor
Yoshihisa Kamo
Yasuhiro Kato
Motoi Aoi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP50042371A priority Critical patent/JPS51117860A/en
Publication of JPS51117860A publication Critical patent/JPS51117860A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
    • H03L7/00—Automatic control of frequency or phase; Synchronisation
    • H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
    • H03L7/07—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop using several loops, e.g. for redundant clock signal generation

Landscapes

  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)

Abstract

PURPOSE:To obtain PLL circuit with small amount of jitter of discrimination window using no extremely long introducing time nor narrow capture range.
JP50042371A 1975-04-09 1975-04-09 Phase lock loop Pending JPS51117860A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50042371A JPS51117860A (en) 1975-04-09 1975-04-09 Phase lock loop

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50042371A JPS51117860A (en) 1975-04-09 1975-04-09 Phase lock loop

Publications (1)

Publication Number Publication Date
JPS51117860A true JPS51117860A (en) 1976-10-16

Family

ID=12634173

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50042371A Pending JPS51117860A (en) 1975-04-09 1975-04-09 Phase lock loop

Country Status (1)

Country Link
JP (1) JPS51117860A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5654952U (en) * 1979-10-01 1981-05-13
JPS60134525A (en) * 1983-12-21 1985-07-17 Matsushita Electric Ind Co Ltd synchronous signal circuit
JPH04313917A (en) * 1991-03-29 1992-11-05 Mitsubishi Electric Corp Double pll device
JPH07283731A (en) * 1995-01-09 1995-10-27 Matsushita Electric Ind Co Ltd Sync signal circuit

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5654952U (en) * 1979-10-01 1981-05-13
JPS60134525A (en) * 1983-12-21 1985-07-17 Matsushita Electric Ind Co Ltd synchronous signal circuit
JPH04313917A (en) * 1991-03-29 1992-11-05 Mitsubishi Electric Corp Double pll device
JPH07283731A (en) * 1995-01-09 1995-10-27 Matsushita Electric Ind Co Ltd Sync signal circuit

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