JPS5246736A - Semiconductor storage circuit - Google Patents

Semiconductor storage circuit

Info

Publication number
JPS5246736A
JPS5246736A JP12181775A JP12181775A JPS5246736A JP S5246736 A JPS5246736 A JP S5246736A JP 12181775 A JP12181775 A JP 12181775A JP 12181775 A JP12181775 A JP 12181775A JP S5246736 A JPS5246736 A JP S5246736A
Authority
JP
Japan
Prior art keywords
output
storage circuit
semiconductor storage
circuit
fet
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12181775A
Other languages
Japanese (ja)
Inventor
Minoru Fukuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP12181775A priority Critical patent/JPS5246736A/en
Publication of JPS5246736A publication Critical patent/JPS5246736A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Read Only Memory (AREA)

Abstract

PURPOSE:Transmission FET is provided between output of voltage division circuit and output lineof memory cell as well as FET which charges the capacity of output circuit between power source terminal and output line is provided respectively. In this way, FAMOS storage circuit of high-speed operation is obtained without any mis-memorization.
JP12181775A 1975-10-11 1975-10-11 Semiconductor storage circuit Pending JPS5246736A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12181775A JPS5246736A (en) 1975-10-11 1975-10-11 Semiconductor storage circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12181775A JPS5246736A (en) 1975-10-11 1975-10-11 Semiconductor storage circuit

Publications (1)

Publication Number Publication Date
JPS5246736A true JPS5246736A (en) 1977-04-13

Family

ID=14820655

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12181775A Pending JPS5246736A (en) 1975-10-11 1975-10-11 Semiconductor storage circuit

Country Status (1)

Country Link
JP (1) JPS5246736A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55165157A (en) * 1979-06-08 1980-12-23 Hisashi Kato Dust collecting electrode plate for electrostatic precipitator
US9030877B2 (en) 2007-08-30 2015-05-12 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55165157A (en) * 1979-06-08 1980-12-23 Hisashi Kato Dust collecting electrode plate for electrostatic precipitator
US9030877B2 (en) 2007-08-30 2015-05-12 Infineon Technologies Ag Memory cell arrangement, method for controlling a memory cell, memory array and electronic device

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