JPS5260071A - Production of semiconductor device - Google Patents

Production of semiconductor device

Info

Publication number
JPS5260071A
JPS5260071A JP50135818A JP13581875A JPS5260071A JP S5260071 A JPS5260071 A JP S5260071A JP 50135818 A JP50135818 A JP 50135818A JP 13581875 A JP13581875 A JP 13581875A JP S5260071 A JPS5260071 A JP S5260071A
Authority
JP
Japan
Prior art keywords
production
semiconductor device
electrode
etching
monitor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP50135818A
Other languages
Japanese (ja)
Other versions
JPS5742222B2 (en
Inventor
Miyoshi Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP50135818A priority Critical patent/JPS5260071A/en
Publication of JPS5260071A publication Critical patent/JPS5260071A/en
Publication of JPS5742222B2 publication Critical patent/JPS5742222B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Manufacturing Of Printed Circuit Boards (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Weting (AREA)
  • ing And Chemical Polishing (AREA)

Abstract

PURPOSE: To prevent over-etching by simultaneously forming a monitor electrode aside from a required protruding electrode via matal layer and assessing the completion of the required etching under the electrode from the dislocation of the monitor electrode from substrate.
COPYRIGHT: (C)1977,JPO&Japio
JP50135818A 1975-11-12 1975-11-12 Production of semiconductor device Granted JPS5260071A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP50135818A JPS5260071A (en) 1975-11-12 1975-11-12 Production of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP50135818A JPS5260071A (en) 1975-11-12 1975-11-12 Production of semiconductor device

Publications (2)

Publication Number Publication Date
JPS5260071A true JPS5260071A (en) 1977-05-18
JPS5742222B2 JPS5742222B2 (en) 1982-09-07

Family

ID=15160514

Family Applications (1)

Application Number Title Priority Date Filing Date
JP50135818A Granted JPS5260071A (en) 1975-11-12 1975-11-12 Production of semiconductor device

Country Status (1)

Country Link
JP (1) JPS5260071A (en)

Also Published As

Publication number Publication date
JPS5742222B2 (en) 1982-09-07

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