JPS5268971A - Method of pretreating adhesion of multiple layers of multiilayer printed circuit board - Google Patents

Method of pretreating adhesion of multiple layers of multiilayer printed circuit board

Info

Publication number
JPS5268971A
JPS5268971A JP14533875A JP14533875A JPS5268971A JP S5268971 A JPS5268971 A JP S5268971A JP 14533875 A JP14533875 A JP 14533875A JP 14533875 A JP14533875 A JP 14533875A JP S5268971 A JPS5268971 A JP S5268971A
Authority
JP
Japan
Prior art keywords
pretreating
adhesion
circuit board
printed circuit
multiple layers
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14533875A
Other languages
Japanese (ja)
Inventor
Kenji Tsukanishi
Masamichi Shimizu
Taketoshi Nakagawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Corp
Original Assignee
Hitachi Chemical Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Chemical Co Ltd filed Critical Hitachi Chemical Co Ltd
Priority to JP14533875A priority Critical patent/JPS5268971A/en
Publication of JPS5268971A publication Critical patent/JPS5268971A/en
Pending legal-status Critical Current

Links

Landscapes

  • Manufacturing Of Printed Wiring (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
JP14533875A 1975-12-05 1975-12-05 Method of pretreating adhesion of multiple layers of multiilayer printed circuit board Pending JPS5268971A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14533875A JPS5268971A (en) 1975-12-05 1975-12-05 Method of pretreating adhesion of multiple layers of multiilayer printed circuit board

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14533875A JPS5268971A (en) 1975-12-05 1975-12-05 Method of pretreating adhesion of multiple layers of multiilayer printed circuit board

Publications (1)

Publication Number Publication Date
JPS5268971A true JPS5268971A (en) 1977-06-08

Family

ID=15382853

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14533875A Pending JPS5268971A (en) 1975-12-05 1975-12-05 Method of pretreating adhesion of multiple layers of multiilayer printed circuit board

Country Status (1)

Country Link
JP (1) JPS5268971A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62242531A (en) * 1986-04-15 1987-10-23 東芝ケミカル株式会社 Blackening treating method of copper-lined laminated board
GB2257714A (en) * 1991-07-16 1993-01-20 Nippon Cmk Kk Treated copper foil for copper laminated board of printed wiring board
US5289630A (en) * 1991-07-22 1994-03-01 Macdermid, Incorporated Process for fabricating multilayer printed circuits

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4873760A (en) * 1971-12-30 1973-10-04

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4873760A (en) * 1971-12-30 1973-10-04

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62242531A (en) * 1986-04-15 1987-10-23 東芝ケミカル株式会社 Blackening treating method of copper-lined laminated board
GB2257714A (en) * 1991-07-16 1993-01-20 Nippon Cmk Kk Treated copper foil for copper laminated board of printed wiring board
US5289630A (en) * 1991-07-22 1994-03-01 Macdermid, Incorporated Process for fabricating multilayer printed circuits

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