JPS54100247A - Test device for logic circuit - Google Patents

Test device for logic circuit

Info

Publication number
JPS54100247A
JPS54100247A JP701678A JP701678A JPS54100247A JP S54100247 A JPS54100247 A JP S54100247A JP 701678 A JP701678 A JP 701678A JP 701678 A JP701678 A JP 701678A JP S54100247 A JPS54100247 A JP S54100247A
Authority
JP
Japan
Prior art keywords
circuit
matrix
card
output
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP701678A
Other languages
Japanese (ja)
Inventor
Takeshi Yasukawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP701678A priority Critical patent/JPS54100247A/en
Publication of JPS54100247A publication Critical patent/JPS54100247A/en
Pending legal-status Critical Current

Links

Landscapes

  • Tests Of Electronic Circuits (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE: To ensure a test for an optional logic card with one unit of the test machine for the logic condition deciding test of the electronic circuit by constituting the input and output signal conversion parts with the wired matrix circuit and doide.
CONSTITUTION: The step signal given from shift register 1 gives the signal voltage to logic card 4 from input buffer circuit 3 via diode matrix 2 which selects the input signal to card 4. The output signals tested through the test program are supplied to output buffer circuit 5 via card 4 then applied to wired matrix 6 where the output signals of circuit 5 are selected. The output signals selected at matrix 6 enter decision circuit 7 to be decided for the coincidence with the step signals sent from register 1, and the decision signals from circuit 7 light up display unit 9 via memory circuit 8. With production of the matrix cards for the input and output, an optional logic card can be checked through a unit of the test machine.
COPYRIGHT: (C)1979,JPO&Japio
JP701678A 1978-01-24 1978-01-24 Test device for logic circuit Pending JPS54100247A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP701678A JPS54100247A (en) 1978-01-24 1978-01-24 Test device for logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP701678A JPS54100247A (en) 1978-01-24 1978-01-24 Test device for logic circuit

Publications (1)

Publication Number Publication Date
JPS54100247A true JPS54100247A (en) 1979-08-07

Family

ID=11654234

Family Applications (1)

Application Number Title Priority Date Filing Date
JP701678A Pending JPS54100247A (en) 1978-01-24 1978-01-24 Test device for logic circuit

Country Status (1)

Country Link
JP (1) JPS54100247A (en)

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