JPS54100676A - Manufacture of semiconductor device - Google Patents

Manufacture of semiconductor device

Info

Publication number
JPS54100676A
JPS54100676A JP673278A JP673278A JPS54100676A JP S54100676 A JPS54100676 A JP S54100676A JP 673278 A JP673278 A JP 673278A JP 673278 A JP673278 A JP 673278A JP S54100676 A JPS54100676 A JP S54100676A
Authority
JP
Japan
Prior art keywords
etching
layer
lamination
taper angle
desirable
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP673278A
Other languages
Japanese (ja)
Inventor
Hatsuo Nakamura
Masaharu Aoyama
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP673278A priority Critical patent/JPS54100676A/en
Publication of JPS54100676A publication Critical patent/JPS54100676A/en
Pending legal-status Critical Current

Links

Landscapes

  • Weting (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

PURPOSE: To obtain a desirable taper angle at the edge of a lamination body by using metal different in etching rate with a fixed etching solution at the time of stacking, adhering and etching a multilayer wiring body on a semiconductor substrate into a desirable pattern.
CONSTITUTION: On Si substrate 1, the wiring layer composed of Al layer 13' Al-Si- Cu layer 14' and Mo layer 15' are stacked and adhered via SiO2 film 12. Then, lamination bodies are formed which have etching rates once, 1.2 to twice and 2.3 to three times as high as that of a mixed solution composed mainly of phosphoric acid, and acetic acid, nitric acid and water as additives, and onto layer 15', photo resist film 16' in a fixed pattern is provided. Through etching using the mixed solution, a taper angle of 20 to 30° is given to lamination bodies on the bais of etching rates. Lastly, film 16' is removed to obtain the desirable lamination wiring body. In this way, the taper angle at the endge can be fixed freely and the multilayer wiring body can also be made highly accurate.
COPYRIGHT: (C)1979,JPO&Japio
JP673278A 1978-01-26 1978-01-26 Manufacture of semiconductor device Pending JPS54100676A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP673278A JPS54100676A (en) 1978-01-26 1978-01-26 Manufacture of semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP673278A JPS54100676A (en) 1978-01-26 1978-01-26 Manufacture of semiconductor device

Publications (1)

Publication Number Publication Date
JPS54100676A true JPS54100676A (en) 1979-08-08

Family

ID=11646400

Family Applications (1)

Application Number Title Priority Date Filing Date
JP673278A Pending JPS54100676A (en) 1978-01-26 1978-01-26 Manufacture of semiconductor device

Country Status (1)

Country Link
JP (1) JPS54100676A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6489436A (en) * 1987-09-30 1989-04-03 Toshiba Corp Manufacture of semiconductor device
US5753535A (en) * 1991-09-18 1998-05-19 Fujitsu Limited Leadframe and resin-sealed semiconductor device

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6489436A (en) * 1987-09-30 1989-04-03 Toshiba Corp Manufacture of semiconductor device
US5753535A (en) * 1991-09-18 1998-05-19 Fujitsu Limited Leadframe and resin-sealed semiconductor device

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