JPS54101291A - Semiconductor memory device - Google Patents

Semiconductor memory device

Info

Publication number
JPS54101291A
JPS54101291A JP724578A JP724578A JPS54101291A JP S54101291 A JPS54101291 A JP S54101291A JP 724578 A JP724578 A JP 724578A JP 724578 A JP724578 A JP 724578A JP S54101291 A JPS54101291 A JP S54101291A
Authority
JP
Japan
Prior art keywords
region
type
base
layer
emitter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP724578A
Other languages
Japanese (ja)
Inventor
Minoru Enomoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP724578A priority Critical patent/JPS54101291A/en
Publication of JPS54101291A publication Critical patent/JPS54101291A/en
Pending legal-status Critical Current

Links

Landscapes

  • Read Only Memory (AREA)
  • Semiconductor Memories (AREA)

Abstract

PURPOSE: To prevent the damage in error, by reducing the write-in power through the increase in the impurity concentration for the base surface part of transistor forming the memory cell.
CONSTITUTION: The common collector layer 2 consisting of the N type layer is formed on the semiconductor substrate 1 consisting of the p type layer, the p+ type base region 3 is formed on the specific part of the collector layer 2 and the emitter region 4 of N+ type is formed at a part of the base region. The implanted layer 5 of N+ type is formed between the substrate 1 and the collector layer 2, and the low resistance region 6 is connected to the implanted layer 5 from the surface of device. The p+ region 7 having comparatively greater impurity concentration is formed at the surface of the base region 3. When pulse current is fed between the emitter 4 and the base 5, since the current concentrates on the P+ type region 7, the junction destruction between the emitter and the base can be achieved with small current.
COPYRIGHT: (C)1979,JPO&Japio
JP724578A 1978-01-27 1978-01-27 Semiconductor memory device Pending JPS54101291A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP724578A JPS54101291A (en) 1978-01-27 1978-01-27 Semiconductor memory device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP724578A JPS54101291A (en) 1978-01-27 1978-01-27 Semiconductor memory device

Publications (1)

Publication Number Publication Date
JPS54101291A true JPS54101291A (en) 1979-08-09

Family

ID=11660618

Family Applications (1)

Application Number Title Priority Date Filing Date
JP724578A Pending JPS54101291A (en) 1978-01-27 1978-01-27 Semiconductor memory device

Country Status (1)

Country Link
JP (1) JPS54101291A (en)

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