JPS54109727A - Memory device - Google Patents
Memory deviceInfo
- Publication number
- JPS54109727A JPS54109727A JP1649378A JP1649378A JPS54109727A JP S54109727 A JPS54109727 A JP S54109727A JP 1649378 A JP1649378 A JP 1649378A JP 1649378 A JP1649378 A JP 1649378A JP S54109727 A JPS54109727 A JP S54109727A
- Authority
- JP
- Japan
- Prior art keywords
- bit
- error correction
- words
- word
- information
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 208000011580 syndromic disease Diseases 0.000 abstract 2
- 150000001875 compounds Chemical class 0.000 abstract 1
Landscapes
- Detection And Correction Of Errors (AREA)
- Techniques For Improving Reliability Of Storages (AREA)
Abstract
PURPOSE: To reduce the hardware quantity of the memory element which is necessary for the error correction bit by growing the syndrome through the decoder against the information read out from the memory element and then disignating the bit position to be corrected for the two-word data information via the corrector circuit.
CONSTITUTION: Writing register 4 holds the writing information equivalent to one word which is given from processor 2, and this writing information is compounded with the reading information equivalent to two words of memory element 7 to be held in compound register 5 in the form of two words. Here, the error correction code is generated from encoder 6 to be memorized in element 7. Then the syndrome is generated from decoder 8 to the information read from element 7, and the bit position to be corrected is designated via corrector circuit 10 for the two-word data. Then the data equivalent to one word, which inverts the bit positions for the two words to send them to processor 2, is held at reading register 11. As a result, the quantity of the hardware can be reduced for element 7 required for the error correction code bit by applying the error correction code bit to the data of plural words.
COPYRIGHT: (C)1979,JPO&Japio
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1649378A JPS54109727A (en) | 1978-02-17 | 1978-02-17 | Memory device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1649378A JPS54109727A (en) | 1978-02-17 | 1978-02-17 | Memory device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS54109727A true JPS54109727A (en) | 1979-08-28 |
Family
ID=11917804
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1649378A Pending JPS54109727A (en) | 1978-02-17 | 1978-02-17 | Memory device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS54109727A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3124281A (en) * | 1964-03-10 | stull |
-
1978
- 1978-02-17 JP JP1649378A patent/JPS54109727A/en active Pending
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US3124281A (en) * | 1964-03-10 | stull |
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