JPS54110449A - Relay - Google Patents

Relay

Info

Publication number
JPS54110449A
JPS54110449A JP1714878A JP1714878A JPS54110449A JP S54110449 A JPS54110449 A JP S54110449A JP 1714878 A JP1714878 A JP 1714878A JP 1714878 A JP1714878 A JP 1714878A JP S54110449 A JPS54110449 A JP S54110449A
Authority
JP
Japan
Prior art keywords
level detection
output
slla
detection circuits
sllb
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1714878A
Other languages
Japanese (ja)
Inventor
Ryoichi Tsukui
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP1714878A priority Critical patent/JPS54110449A/en
Publication of JPS54110449A publication Critical patent/JPS54110449A/en
Pending legal-status Critical Current

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  • Emergency Protection Circuit Devices (AREA)

Abstract

PURPOSE: To automatically and accurately detect the detection level variation of a realy with level detection circuits and its complete fault mode by checking the output unmatch of the respective level detection circuits.
CONSTITUTION: When the respective level detection values of the level detection circuits SLLA and SLLB are equal, the output of the AND gate AND (A) remains 0 since the input current of the respective level detection circuits SLLA and SLLB is common in the cheching AC power supply ACT. Thus, the input of the timer circuit TA is always set to 0 and no fault output is detected from the relay RYA. If the level detection value of the level detection circuit SLLA rises due to any causes, the duty of this output square wave decreases. Accordingly, the AND gate AND (A) outputs pulses. When these pulse widths exceed the specified value, the timer circuit TA operates and the fault output is detected from the relay RYA. This applies to the case where the level detection where decreases.
COPYRIGHT: (C)1979,JPO&Japio
JP1714878A 1978-02-17 1978-02-17 Relay Pending JPS54110449A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1714878A JPS54110449A (en) 1978-02-17 1978-02-17 Relay

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1714878A JPS54110449A (en) 1978-02-17 1978-02-17 Relay

Publications (1)

Publication Number Publication Date
JPS54110449A true JPS54110449A (en) 1979-08-29

Family

ID=11935896

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1714878A Pending JPS54110449A (en) 1978-02-17 1978-02-17 Relay

Country Status (1)

Country Link
JP (1) JPS54110449A (en)

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