JPS54112181A - Nonvolatile semiconductor memory unit - Google Patents
Nonvolatile semiconductor memory unitInfo
- Publication number
- JPS54112181A JPS54112181A JP2010478A JP2010478A JPS54112181A JP S54112181 A JPS54112181 A JP S54112181A JP 2010478 A JP2010478 A JP 2010478A JP 2010478 A JP2010478 A JP 2010478A JP S54112181 A JPS54112181 A JP S54112181A
- Authority
- JP
- Japan
- Prior art keywords
- region
- gate layer
- memory element
- type
- diffusion
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/68—Floating-gate IGFETs
- H10D30/681—Floating-gate IGFETs having only two programming levels
- H10D30/684—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection
- H10D30/686—Floating-gate IGFETs having only two programming levels programmed by hot carrier injection using hot carriers produced by avalanche breakdown of PN junctions, e.g. floating gate avalanche injection MOS [FAMOS]
Landscapes
- Semiconductor Memories (AREA)
- Non-Volatile Memory (AREA)
Abstract
PURPOSE:To make a memory element operate stably with no latch-up phenomenon even when combined with a peripheral device such as a C-MOSIC circuit by composing the memory element of a P-channel FET of lamination gate structure and by allowing it to operate under fixed conditions. CONSTITUTION:In N<->-type Si substrate 1, P<+>-type drain region 2a and P<+>-type source region 2b are formed by diffusion, and shallow N-type region 9 touching region 2a is also formed by diffusion, Next, 1st polycrystal Si gate layer 4 on region 9 and SiO2 film 3 including 2nd poly-crystal Si gate layer 8 expanding onto region 2b are both adhered over the entire surface and after an opening is made, Al electrodes 5 are fitted to regions 2a and 2b, and gate layer 8. In this way, since region 9 of higher impurity density than that of substrate 1 is provided, the threshold level of the memory element becomes high and even if a voltage of approximate 5V is applied to gate layer 8, no channel is generated. Further, the avalanch breakdown voltage of the PN junction between regions 9 and 2a decreases and the write voltage also decreases.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2010478A JPS54112181A (en) | 1978-02-22 | 1978-02-22 | Nonvolatile semiconductor memory unit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2010478A JPS54112181A (en) | 1978-02-22 | 1978-02-22 | Nonvolatile semiconductor memory unit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS54112181A true JPS54112181A (en) | 1979-09-01 |
Family
ID=12017795
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2010478A Pending JPS54112181A (en) | 1978-02-22 | 1978-02-22 | Nonvolatile semiconductor memory unit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS54112181A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5812367A (en) * | 1981-07-16 | 1983-01-24 | Matsushita Electronics Corp | semiconductor storage device |
-
1978
- 1978-02-22 JP JP2010478A patent/JPS54112181A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5812367A (en) * | 1981-07-16 | 1983-01-24 | Matsushita Electronics Corp | semiconductor storage device |
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