JPS5434663A - High-frequency/high-output integrated circuit - Google Patents

High-frequency/high-output integrated circuit

Info

Publication number
JPS5434663A
JPS5434663A JP10093177A JP10093177A JPS5434663A JP S5434663 A JPS5434663 A JP S5434663A JP 10093177 A JP10093177 A JP 10093177A JP 10093177 A JP10093177 A JP 10093177A JP S5434663 A JPS5434663 A JP S5434663A
Authority
JP
Japan
Prior art keywords
frequency
integrated circuit
conductor film
output integrated
dielectric layer
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10093177A
Other languages
Japanese (ja)
Inventor
Hidehiko Kato
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10093177A priority Critical patent/JPS5434663A/en
Publication of JPS5434663A publication Critical patent/JPS5434663A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03F—AMPLIFIERS
    • H03F3/00—Amplifiers with only discharge tubes or only semiconductor devices as amplifying elements
    • H03F3/60—Amplifiers in which coupling networks have distributed constants, e.g. with waveguide resonators
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/753—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between laterally-adjacent chips
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
  • Microwave Amplifiers (AREA)

Abstract

PURPOSE:To obtain a circuit which can extract the output without imparing the property of the high-frequency solid element, by coating the surface of the dielectric substrate with the earth conductor film of a fixed thickness, forming a dielectric layer of a fixed thickness on the conductor film and furthermore forming the conductor film pattern in a fixed shape on the dielectric layer.
JP10093177A 1977-08-22 1977-08-22 High-frequency/high-output integrated circuit Pending JPS5434663A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10093177A JPS5434663A (en) 1977-08-22 1977-08-22 High-frequency/high-output integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10093177A JPS5434663A (en) 1977-08-22 1977-08-22 High-frequency/high-output integrated circuit

Publications (1)

Publication Number Publication Date
JPS5434663A true JPS5434663A (en) 1979-03-14

Family

ID=14287085

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10093177A Pending JPS5434663A (en) 1977-08-22 1977-08-22 High-frequency/high-output integrated circuit

Country Status (1)

Country Link
JP (1) JPS5434663A (en)

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