JPS5448448A - Inspection system of memory error - Google Patents

Inspection system of memory error

Info

Publication number
JPS5448448A
JPS5448448A JP11536977A JP11536977A JPS5448448A JP S5448448 A JPS5448448 A JP S5448448A JP 11536977 A JP11536977 A JP 11536977A JP 11536977 A JP11536977 A JP 11536977A JP S5448448 A JPS5448448 A JP S5448448A
Authority
JP
Japan
Prior art keywords
failure
bit
range
address information
display
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11536977A
Other languages
Japanese (ja)
Inventor
Takahiko Ogita
Masato Hashimoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11536977A priority Critical patent/JPS5448448A/en
Publication of JPS5448448A publication Critical patent/JPS5448448A/en
Pending legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To accurately display the range of failure of the memory unit with a simple constitution, by providing the storage means storing the syndrome bit and the address information and by providing the comparison means and the means for the failure range display.
CONSTITUTION: In the memory unit having the n bit error correction and the n bit error detection function, registers 3-1 to 3-4 storing the bit and address information on the syndrome bit line la, substrate selection address, chip selection address and cell selection address lines lb to ld. Further, if n-bit error is taken place, the present syndrome bit and the address information are compared with them held in the registers 3-1 to 3-4 already by the comparators 4-1 to 4-4, and they are displayed on the display unit by classifying the range of failure with one cell failure, one chip failure, in-substrate failure of bit system failure by the failure range display circuit 6
COPYRIGHT: (C)1979,JPO&Japio
JP11536977A 1977-09-26 1977-09-26 Inspection system of memory error Pending JPS5448448A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11536977A JPS5448448A (en) 1977-09-26 1977-09-26 Inspection system of memory error

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11536977A JPS5448448A (en) 1977-09-26 1977-09-26 Inspection system of memory error

Publications (1)

Publication Number Publication Date
JPS5448448A true JPS5448448A (en) 1979-04-17

Family

ID=14660810

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11536977A Pending JPS5448448A (en) 1977-09-26 1977-09-26 Inspection system of memory error

Country Status (1)

Country Link
JP (1) JPS5448448A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114461476A (en) * 2022-02-14 2022-05-10 深圳源创存储科技有限公司 Memory bank fault detection method, device and system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN114461476A (en) * 2022-02-14 2022-05-10 深圳源创存储科技有限公司 Memory bank fault detection method, device and system
CN114461476B (en) * 2022-02-14 2023-09-26 深圳源创存储科技有限公司 A memory module fault detection method, device and system

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