JPS5449010A - Removing system for phase indeterminacy - Google Patents

Removing system for phase indeterminacy

Info

Publication number
JPS5449010A
JPS5449010A JP11510777A JP11510777A JPS5449010A JP S5449010 A JPS5449010 A JP S5449010A JP 11510777 A JP11510777 A JP 11510777A JP 11510777 A JP11510777 A JP 11510777A JP S5449010 A JPS5449010 A JP S5449010A
Authority
JP
Japan
Prior art keywords
phase
output
indeterminacy
word
supplied
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11510777A
Other languages
Japanese (ja)
Inventor
Tadayoshi Kato
Tadashi Sekizawa
Shunroku Sasaki
Yoshitoshi Tsuji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP11510777A priority Critical patent/JPS5449010A/en
Publication of JPS5449010A publication Critical patent/JPS5449010A/en
Pending legal-status Critical Current

Links

Landscapes

  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE: To establish both carrier phase synchronism and word cynchronism at the same time, by controlling a word phase and carrier phase by attaining the synchronization so that the vector through the combination of time slots will not be detected at the reception side.
CONSTITUTION: In the phase indeterminacy removing system which removes carrier-phase indeterminacy and word-phase indeterminacy on the three-phase modulation system, a three-phase modulation input is supplied to three-phases modulator 1, modulated data (d1), (d2) and (d3) are applied to occurrence establishing discriminators 4a, 4b and 4c respectively, and respective outputs are applied to change-over switch driver 5. Then, the output of driver 5 is applied to change- over switch 3 supplied with modulated data (d1) to (d3), and also to synchronous signal generator 2 supplied with words from modulator 1, and the output of generator 2 is applied to discriminators 4a to 4c. Next, the output of switch 3 and the output of generator 2 are both applied to ternary-binary converter 6, and the combination of time slots is so made that the vector will not be detected at the reception side
COPYRIGHT: (C)1979,JPO&Japio
JP11510777A 1977-09-27 1977-09-27 Removing system for phase indeterminacy Pending JPS5449010A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11510777A JPS5449010A (en) 1977-09-27 1977-09-27 Removing system for phase indeterminacy

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11510777A JPS5449010A (en) 1977-09-27 1977-09-27 Removing system for phase indeterminacy

Publications (1)

Publication Number Publication Date
JPS5449010A true JPS5449010A (en) 1979-04-18

Family

ID=14654396

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11510777A Pending JPS5449010A (en) 1977-09-27 1977-09-27 Removing system for phase indeterminacy

Country Status (1)

Country Link
JP (1) JPS5449010A (en)

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