JPS5451742A - Information processor containing intermediate language statisize mechanism - Google Patents

Information processor containing intermediate language statisize mechanism

Info

Publication number
JPS5451742A
JPS5451742A JP11814077A JP11814077A JPS5451742A JP S5451742 A JPS5451742 A JP S5451742A JP 11814077 A JP11814077 A JP 11814077A JP 11814077 A JP11814077 A JP 11814077A JP S5451742 A JPS5451742 A JP S5451742A
Authority
JP
Japan
Prior art keywords
intermediate language
program
statisize
unit
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP11814077A
Other languages
Japanese (ja)
Inventor
Yasuhito Wakasugi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP11814077A priority Critical patent/JPS5451742A/en
Publication of JPS5451742A publication Critical patent/JPS5451742A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To shorten the process time for the intermediate language by changing the statisize part which forms part of whole of the interpretation routine of the intermediate language into hardware.
CONSTITUTION: Processor 3 is connected to direct memory access DMA control part 4, intermediate statisize unit 5 and main memory 6 via the memory bus and furthermore unit 5 is connected to processor 3 and part 4 via DMA control bus 7. When the execution of the intermediate language program is designated via the system program, processor 3 shifts the program control to intermediate language interpretation control program within memory 6 and issues the input/output order to start unit 5. Then order word fetch control part 22 reads out operation code part 11 of the order word set by the intermediate language, and prescibed address renewal part 25 renews intermediate language program counter 15 to the head address of the next order word. And these actions are carried out directly by the memory access of unit 5 via part 4
COPYRIGHT: (C)1979,JPO&Japio
JP11814077A 1977-09-30 1977-09-30 Information processor containing intermediate language statisize mechanism Pending JPS5451742A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP11814077A JPS5451742A (en) 1977-09-30 1977-09-30 Information processor containing intermediate language statisize mechanism

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11814077A JPS5451742A (en) 1977-09-30 1977-09-30 Information processor containing intermediate language statisize mechanism

Publications (1)

Publication Number Publication Date
JPS5451742A true JPS5451742A (en) 1979-04-23

Family

ID=14729046

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11814077A Pending JPS5451742A (en) 1977-09-30 1977-09-30 Information processor containing intermediate language statisize mechanism

Country Status (1)

Country Link
JP (1) JPS5451742A (en)

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