JPS5518718A - Interruption system for specific program - Google Patents

Interruption system for specific program

Info

Publication number
JPS5518718A
JPS5518718A JP9026878A JP9026878A JPS5518718A JP S5518718 A JPS5518718 A JP S5518718A JP 9026878 A JP9026878 A JP 9026878A JP 9026878 A JP9026878 A JP 9026878A JP S5518718 A JPS5518718 A JP S5518718A
Authority
JP
Japan
Prior art keywords
circuit
timing signal
memory
signal
jump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9026878A
Other languages
Japanese (ja)
Inventor
Takashi Bishiyari
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP9026878A priority Critical patent/JPS5518718A/en
Publication of JPS5518718A publication Critical patent/JPS5518718A/en
Pending legal-status Critical Current

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Abstract

PURPOSE: To obtain a specific-program interruption system which can remove complexity in terms of software and hardware, by making it possible to use forcibly CPU from the outside without using an interrupting method.
CONSTITUTION: Switch 9 connected to timing control circuit 10 in intrruption processing circuit 5 is closed. As a result, circuit 10 is supplied with fetch timing signal A from CPU1 and memory inhibition signal B inhibiting access to memory 2 is transferred. Further, circuit 10 transfers timing signal A to address latch circuit 7 before a jump instruction is generated and timing signal C for storing a program after the interruption is transferred to memory. On the generation of the jump instruction, circuit 10 sends timing signal A to jump code generating circuit 11. On receiving signal A, circuit 11 transfers a jump code to data bus 4.
COPYRIGHT: (C)1980,JPO&Japio
JP9026878A 1978-07-24 1978-07-24 Interruption system for specific program Pending JPS5518718A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9026878A JPS5518718A (en) 1978-07-24 1978-07-24 Interruption system for specific program

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9026878A JPS5518718A (en) 1978-07-24 1978-07-24 Interruption system for specific program

Publications (1)

Publication Number Publication Date
JPS5518718A true JPS5518718A (en) 1980-02-09

Family

ID=13993750

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9026878A Pending JPS5518718A (en) 1978-07-24 1978-07-24 Interruption system for specific program

Country Status (1)

Country Link
JP (1) JPS5518718A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56155451A (en) * 1980-04-30 1981-12-01 Sharp Corp Electronic computer
JPS61103255A (en) * 1984-10-26 1986-05-21 Nec Corp Data collection system in case of fault
JPH01263732A (en) * 1988-04-14 1989-10-20 Sharp Corp Special action processing system for microprocessor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56155451A (en) * 1980-04-30 1981-12-01 Sharp Corp Electronic computer
JPS61103255A (en) * 1984-10-26 1986-05-21 Nec Corp Data collection system in case of fault
JPH01263732A (en) * 1988-04-14 1989-10-20 Sharp Corp Special action processing system for microprocessor

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