JPS5459083A - Double-sided pattern forming method for semiconductor wafer - Google Patents

Double-sided pattern forming method for semiconductor wafer

Info

Publication number
JPS5459083A
JPS5459083A JP12543877A JP12543877A JPS5459083A JP S5459083 A JPS5459083 A JP S5459083A JP 12543877 A JP12543877 A JP 12543877A JP 12543877 A JP12543877 A JP 12543877A JP S5459083 A JPS5459083 A JP S5459083A
Authority
JP
Japan
Prior art keywords
pattern
resist
hole
double
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12543877A
Other languages
Japanese (ja)
Inventor
Hiroshi Okuda
Shinichi Iguchi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Electric Industries Ltd
Original Assignee
Sumitomo Electric Industries Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Electric Industries Ltd filed Critical Sumitomo Electric Industries Ltd
Priority to JP12543877A priority Critical patent/JPS5459083A/en
Publication of JPS5459083A publication Critical patent/JPS5459083A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G03—PHOTOGRAPHY; CINEMATOGRAPHY; ANALOGOUS TECHNIQUES USING WAVES OTHER THAN OPTICAL WAVES; ELECTROGRAPHY; HOLOGRAPHY
    • G03F—PHOTOMECHANICAL PRODUCTION OF TEXTURED OR PATTERNED SURFACES, e.g. FOR PRINTING, FOR PROCESSING OF SEMICONDUCTOR DEVICES; MATERIALS THEREFOR; ORIGINALS THEREFOR; APPARATUS SPECIALLY ADAPTED THEREFOR
    • G03F9/00—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically
    • G03F9/70—Registration or positioning of originals, masks, frames, photographic sheets or textured or patterned surfaces, e.g. automatically for microlithography

Landscapes

  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Exposure And Positioning Against Photoresist Photosensitive Materials (AREA)

Abstract

PURPOSE: To secure easy formation of the pattern on both surfaces of the substrate in a high relative positioning accuracy based on more than one pierced hole which are fomed on the substrate through the anisotropic etching.
CONSTITUTION: More than one unit of window-drilled pattern 12 of resist 21 are formed at the end of single surface 13 of GaAs substrate 11. Resist 41 is coated on the other surface 22 piercing through reference hole 42 featuring the flat side wall, with the anisotropic etching applied with H3PO4+H2O2-group etching solution. Thus, the relative position relation is secured between window 43 and 44 with high accuracy and reproducibility. After this, the resist is removed, and the mask positioning to surface 13 is performed with coincidence between hole 42 and mask matching pattern 71. And resist pattern 72 is formed. On surface 22, a coincidence is secured between hole 42 and mask matching pattern 81 to from resist pattern 82. Thus,the relative positioning between pafttern 72 and 82 can be regulated in a high accuracy
COPYRIGHT: (C)1979,JPO&Japio
JP12543877A 1977-10-19 1977-10-19 Double-sided pattern forming method for semiconductor wafer Pending JPS5459083A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12543877A JPS5459083A (en) 1977-10-19 1977-10-19 Double-sided pattern forming method for semiconductor wafer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12543877A JPS5459083A (en) 1977-10-19 1977-10-19 Double-sided pattern forming method for semiconductor wafer

Publications (1)

Publication Number Publication Date
JPS5459083A true JPS5459083A (en) 1979-05-12

Family

ID=14910082

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12543877A Pending JPS5459083A (en) 1977-10-19 1977-10-19 Double-sided pattern forming method for semiconductor wafer

Country Status (1)

Country Link
JP (1) JPS5459083A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6052048A (en) * 1983-06-27 1985-03-23 テレタイプ　コ−ポレ−シヨン Method of producing integrated circuit device
JPS6052047A (en) * 1983-06-27 1985-03-23 テレタイプ　コ−ポレ−シヨン Method of producing integrated circuit device
JPS6052046A (en) * 1983-06-27 1985-03-23 テレタイプ　コ−ポレ−シヨン Method of producing integrated circuit device
JPS62114222A (en) * 1985-11-14 1987-05-26 Hitachi Ltd Exposing apparatus
JPS6324617A (en) * 1986-07-17 1988-02-02 Yokogawa Electric Corp Method for double sided exposure of wafer
JPH01214040A (en) * 1988-02-22 1989-08-28 Nec Corp Manufacture of semiconductor integrated circuit
JP2003057853A (en) * 2001-08-08 2003-02-28 Orc Mfg Co Ltd Alignment mark, aligning mechanism and method for aligning

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6052048A (en) * 1983-06-27 1985-03-23 テレタイプ　コ−ポレ−シヨン Method of producing integrated circuit device
JPS6052047A (en) * 1983-06-27 1985-03-23 テレタイプ　コ−ポレ−シヨン Method of producing integrated circuit device
JPS6052046A (en) * 1983-06-27 1985-03-23 テレタイプ　コ−ポレ−シヨン Method of producing integrated circuit device
JPS62114222A (en) * 1985-11-14 1987-05-26 Hitachi Ltd Exposing apparatus
JPS6324617A (en) * 1986-07-17 1988-02-02 Yokogawa Electric Corp Method for double sided exposure of wafer
JPH01214040A (en) * 1988-02-22 1989-08-28 Nec Corp Manufacture of semiconductor integrated circuit
JP2003057853A (en) * 2001-08-08 2003-02-28 Orc Mfg Co Ltd Alignment mark, aligning mechanism and method for aligning

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