JPS5465436A - Rom checking system - Google Patents

Rom checking system

Info

Publication number
JPS5465436A
JPS5465436A JP13222077A JP13222077A JPS5465436A JP S5465436 A JPS5465436 A JP S5465436A JP 13222077 A JP13222077 A JP 13222077A JP 13222077 A JP13222077 A JP 13222077A JP S5465436 A JPS5465436 A JP S5465436A
Authority
JP
Japan
Prior art keywords
address
ram13
rom
ram
test
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP13222077A
Other languages
Japanese (ja)
Other versions
JPS6012661B2 (en
Inventor
Tomohiro Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Casio Computer Co Ltd
Original Assignee
Casio Computer Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Casio Computer Co Ltd filed Critical Casio Computer Co Ltd
Priority to JP52132220A priority Critical patent/JPS6012661B2/en
Publication of JPS5465436A publication Critical patent/JPS5465436A/en
Publication of JPS6012661B2 publication Critical patent/JPS6012661B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Read Only Memory (AREA)

Abstract

PURPOSE: To ensure the check for the function of ROM incorporated into LSI with no addition of the checking terminal, by memorizing previously the different numerial value in each address of RAM, designating the address of RAM by the output of ROM, and reading out the contents of the address to outside to be checked.
CONSTITUTION: The logic circuit performs the arithmetic control through the control by ROM which memorizes the address of RAM 13 plus various instructions. In such logic circuit, the different prescribed data are memorized previously in each address of RAM13 , and the test signal is supplied to terminal 23 when carrying out a test. And AND circuit 26 is closed via inverter 27 to inhibit the writing to RAM13, and RAM13 is kept under the reading mode. The fixed address data are given to ROM11 via address control part, and at the same time the test address control system of RAM13 is actuated via gate group 25. Thus, the necessary data is read out to external tester 28 through RAM13.
COPYRIGHT: (C)1979,JPO&Japio
JP52132220A 1977-11-04 1977-11-04 ROM check method Expired JPS6012661B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52132220A JPS6012661B2 (en) 1977-11-04 1977-11-04 ROM check method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52132220A JPS6012661B2 (en) 1977-11-04 1977-11-04 ROM check method

Publications (2)

Publication Number Publication Date
JPS5465436A true JPS5465436A (en) 1979-05-26
JPS6012661B2 JPS6012661B2 (en) 1985-04-02

Family

ID=15076188

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52132220A Expired JPS6012661B2 (en) 1977-11-04 1977-11-04 ROM check method

Country Status (1)

Country Link
JP (1) JPS6012661B2 (en)

Also Published As

Publication number Publication date
JPS6012661B2 (en) 1985-04-02

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