JPS5476332A - Training counter - Google Patents

Training counter

Info

Publication number
JPS5476332A
JPS5476332A JP14187877A JP14187877A JPS5476332A JP S5476332 A JPS5476332 A JP S5476332A JP 14187877 A JP14187877 A JP 14187877A JP 14187877 A JP14187877 A JP 14187877A JP S5476332 A JPS5476332 A JP S5476332A
Authority
JP
Japan
Prior art keywords
counter
flag
training
exercise
control section
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14187877A
Other languages
Japanese (ja)
Inventor
Tetsuyuki Nakano
Naoki Kuramoto
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Omron Corp
Original Assignee
Omron Tateisi Electronics Co
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Omron Tateisi Electronics Co filed Critical Omron Tateisi Electronics Co
Priority to JP14187877A priority Critical patent/JPS5476332A/en
Publication of JPS5476332A publication Critical patent/JPS5476332A/en
Pending legal-status Critical Current

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  • Measurement Of Unknown Time Intervals (AREA)

Abstract

PURPOSE: To provide a training counter capable of automatically memorizing the quantity of exercise on every day of taking exrecise by providing a date setter and a memorizing device.
CONSTITUTION: The training counter comprises a mat switch 1, which detects the steps of one who takes exercise, an operation panel 2, a control section 3, a memory device 4 and a printer 5. An approach senser is buried in the mat switch 1 to detect the action at every step of one who takes exercise, and the output thereof is coverted into a unit pulse by a waveform shaping device 6 and delivers the same to a step number counter 7, where the number of steps is counted. A counter 13 counting the operation times of a date setting key 10 is provided in the control section 3, and flag 14 corresponding to the counted valve of the counter 13 is set. An address setting section 15 accepts the state of flag 14, and designates address to the memory device 4.
COPYRIGHT: (C)1979,JPO&Japio
JP14187877A 1977-11-26 1977-11-26 Training counter Pending JPS5476332A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14187877A JPS5476332A (en) 1977-11-26 1977-11-26 Training counter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14187877A JPS5476332A (en) 1977-11-26 1977-11-26 Training counter

Publications (1)

Publication Number Publication Date
JPS5476332A true JPS5476332A (en) 1979-06-18

Family

ID=15302255

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14187877A Pending JPS5476332A (en) 1977-11-26 1977-11-26 Training counter

Country Status (1)

Country Link
JP (1) JPS5476332A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57180972A (en) * 1981-04-30 1982-11-08 Oishi Hajime Balance table apparatus
JPH0263165U (en) * 1988-10-26 1990-05-11

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5090432A (en) * 1973-12-07 1975-07-19

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5090432A (en) * 1973-12-07 1975-07-19

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57180972A (en) * 1981-04-30 1982-11-08 Oishi Hajime Balance table apparatus
JPH0263165U (en) * 1988-10-26 1990-05-11

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