JPS5477548A - Computer control unit - Google Patents

Computer control unit

Info

Publication number
JPS5477548A
JPS5477548A JP14486677A JP14486677A JPS5477548A JP S5477548 A JPS5477548 A JP S5477548A JP 14486677 A JP14486677 A JP 14486677A JP 14486677 A JP14486677 A JP 14486677A JP S5477548 A JPS5477548 A JP S5477548A
Authority
JP
Japan
Prior art keywords
order
write
control unit
ram2
execution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14486677A
Other languages
Japanese (ja)
Inventor
Toshiro Ishihara
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP14486677A priority Critical patent/JPS5477548A/en
Publication of JPS5477548A publication Critical patent/JPS5477548A/en
Pending legal-status Critical Current

Links

Landscapes

  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To give the decision for the state on the program by having the checking for the write order to RAM of the store order or the like in terms of the hardware and then giving the waiting stste to CPU after execution of the write subject location address via the switch of the control panel, etc.
CONSTITUTION: A check is given to the write order to RAM2, I/03 of the store order or the like in terms of the hardware, and then the write subject location address is set up via the switch of control panel 6, etc. Then CPU1 is set under the waiting state after execution of the order. Thus, in which point on the program the flag to RAM2 is set or reset or where the set signal and the reset signal are delivered to I/03 can be decided at the level of the control unit.
COPYRIGHT: (C)1979,JPO&Japio
JP14486677A 1977-12-02 1977-12-02 Computer control unit Pending JPS5477548A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14486677A JPS5477548A (en) 1977-12-02 1977-12-02 Computer control unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14486677A JPS5477548A (en) 1977-12-02 1977-12-02 Computer control unit

Publications (1)

Publication Number Publication Date
JPS5477548A true JPS5477548A (en) 1979-06-21

Family

ID=15372207

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14486677A Pending JPS5477548A (en) 1977-12-02 1977-12-02 Computer control unit

Country Status (1)

Country Link
JP (1) JPS5477548A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59151250A (en) * 1983-02-17 1984-08-29 Omron Tateisi Electronics Co Debugging device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59151250A (en) * 1983-02-17 1984-08-29 Omron Tateisi Electronics Co Debugging device

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