JPS5523563A - Computer system - Google Patents

Computer system

Info

Publication number
JPS5523563A
JPS5523563A JP9612978A JP9612978A JPS5523563A JP S5523563 A JPS5523563 A JP S5523563A JP 9612978 A JP9612978 A JP 9612978A JP 9612978 A JP9612978 A JP 9612978A JP S5523563 A JPS5523563 A JP S5523563A
Authority
JP
Japan
Prior art keywords
address
output
bus
simulation
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9612978A
Other languages
Japanese (ja)
Inventor
Ikuo Masuda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP9612978A priority Critical patent/JPS5523563A/en
Publication of JPS5523563A publication Critical patent/JPS5523563A/en
Pending legal-status Critical Current

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  • Programmable Controllers (AREA)

Abstract

PURPOSE: To facilitate simulation of I/O by storing previously a position, where I/O should be simulated, and making it possible to designate contents of I/O forcedly when this position agrees with the address of an I/O bus.
CONSTITUTION: Processing unit 1 in the swquence controller outputs the address of I/O periodically; and in case of data input, since the input which I/O circuit 2 puts on the bus appears after a bus delay time, it is fetched. In case of output, unit 1 generates strobe and writes it in I/O corcuit 2. When the address to be monitored which is written in simulation circuit 4 agrees with the address given from processing unit 1, input or output is generated forcedly in the output of a ROM in simulation unit 4 and effects the same function as a primary I/O. Thus, a forced I/O can be designated at an arbitrary point simply.
COPYRIGHT: (C)1980,JPO&Japio
JP9612978A 1978-08-09 1978-08-09 Computer system Pending JPS5523563A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9612978A JPS5523563A (en) 1978-08-09 1978-08-09 Computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9612978A JPS5523563A (en) 1978-08-09 1978-08-09 Computer system

Publications (1)

Publication Number Publication Date
JPS5523563A true JPS5523563A (en) 1980-02-20

Family

ID=14156767

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9612978A Pending JPS5523563A (en) 1978-08-09 1978-08-09 Computer system

Country Status (1)

Country Link
JP (1) JPS5523563A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5984905A (en) * 1982-08-27 1984-05-16 フイリツプス・ペトロリユ−ム・コンパニ− Olefin polymerization catalyst, manufacture and use
JPH0895611A (en) * 1994-09-28 1996-04-12 Toshiba Corp Programmable controller and its maintenance tool

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5984905A (en) * 1982-08-27 1984-05-16 フイリツプス・ペトロリユ−ム・コンパニ− Olefin polymerization catalyst, manufacture and use
JPH0895611A (en) * 1994-09-28 1996-04-12 Toshiba Corp Programmable controller and its maintenance tool

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