JPS5477585A - Semiconductor device - Google Patents

Abstract

PURPOSE: To effectively block larger current by newly providing a p₃ laye to an N^- layer to form the main path of control current and forming a p₂ layer to a high resistance bias circuit.

CONSTITUTION: When a power source EGF is inserted between P₃ and N⁺ and current is supplied from P₃ to N^- when current is being flowed in the P₁N^-N⁺ direction by a power source E₀ and load R with the P₁ layer as a positive polarity, then the voltage drop of the N^- layer decreases and the allowable current between AK increases. To cut off the load current, the power source EGF is removed and EGR is applied between N⁺N^-P₃. The current flows through P₁-N^--P₃-G₂-EGR-E₀-R- A-P₁. When a switch S₁ is turned ON at the same instant of a swtich S₂ or with a delay for a specified item, current is supplied to P₁N^-P₂ as well and the current of P₁N^- is cut off. When the reverse bias of this N^-P₂ is increased, the depletion layers DL₂, DL₃ around P₂, P₃ contact and P₁N^- and N⁺ are perfectly cut off. With this construction, the P₂ spacing may be increased and the N⁺ layer may be widened to increase current capacity and virtually obviate the flow of current in the circuit of the switch S₁ and therefore the high resistance high voltage circuit may be constructed with the relatively small power source ER.

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