JPS5478036A - Control system of multiplexing memory unit - Google Patents

Control system of multiplexing memory unit

Info

Publication number
JPS5478036A
JPS5478036A JP14505077A JP14505077A JPS5478036A JP S5478036 A JPS5478036 A JP S5478036A JP 14505077 A JP14505077 A JP 14505077A JP 14505077 A JP14505077 A JP 14505077A JP S5478036 A JPS5478036 A JP S5478036A
Authority
JP
Japan
Prior art keywords
memory
address
units
cpu
memory unit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14505077A
Other languages
Japanese (ja)
Other versions
JPS5831680B2 (en
Inventor
Atomi Noguchi
Toshiyuki Ide
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP52145050A priority Critical patent/JPS5831680B2/en
Publication of JPS5478036A publication Critical patent/JPS5478036A/en
Publication of JPS5831680B2 publication Critical patent/JPS5831680B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)

Abstract

PURPOSE: To improve a reliability of a unit with making it possible to check addresses in a multiplexing memory unit such as a duplexing one by checking addresses by comparing the address transferred to the memory unit side in reading or writing.
CONSTITUTION: In the system where data exchanged between CPU 1 and memory units 2 and 3 is stored in plural multiplexed memory units 2 and 3 as memory information, memory interface control circuits 7, 8 and 9 are provided between CPU 1 and units 2 and 3. This control circuit 7 is provided with address comparison and collating circuits 27 and 28 which compare the memory address for accessing units 2 and 3, which is obtained on a basis of the source address transmitted from CPU 1, and the source address. When both addresses agree with each other in collating circuits 27 and 28, the memory address is decided as a correct address, and otherwise, the read or write destination is decided as an error.
COPYRIGHT: (C)1979,JPO&Japio
JP52145050A 1977-12-05 1977-12-05 Control method for multiplexed storage device Expired JPS5831680B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP52145050A JPS5831680B2 (en) 1977-12-05 1977-12-05 Control method for multiplexed storage device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP52145050A JPS5831680B2 (en) 1977-12-05 1977-12-05 Control method for multiplexed storage device

Publications (2)

Publication Number Publication Date
JPS5478036A true JPS5478036A (en) 1979-06-21
JPS5831680B2 JPS5831680B2 (en) 1983-07-07

Family

ID=15376215

Family Applications (1)

Application Number Title Priority Date Filing Date
JP52145050A Expired JPS5831680B2 (en) 1977-12-05 1977-12-05 Control method for multiplexed storage device

Country Status (1)

Country Link
JP (1) JPS5831680B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59170974U (en) * 1983-04-30 1984-11-15 東洋ハ−ネス株式会社 connector housing
JPS6375967U (en) * 1987-06-16 1988-05-20

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4869439A (en) * 1971-12-21 1973-09-20
JPS5211845A (en) * 1975-07-18 1977-01-29 Fujitsu Ltd Address information check system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS4869439A (en) * 1971-12-21 1973-09-20
JPS5211845A (en) * 1975-07-18 1977-01-29 Fujitsu Ltd Address information check system

Also Published As

Publication number Publication date
JPS5831680B2 (en) 1983-07-07

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