JPS5481738A - Multiplex interruption control circuit - Google Patents

Multiplex interruption control circuit

Info

Publication number
JPS5481738A
JPS5481738A JP15022377A JP15022377A JPS5481738A JP S5481738 A JPS5481738 A JP S5481738A JP 15022377 A JP15022377 A JP 15022377A JP 15022377 A JP15022377 A JP 15022377A JP S5481738 A JPS5481738 A JP S5481738A
Authority
JP
Japan
Prior art keywords
registers
interruption
reset signal
signal
inputted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15022377A
Other languages
Japanese (ja)
Inventor
Tetsuo Yonezawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP15022377A priority Critical patent/JPS5481738A/en
Publication of JPS5481738A publication Critical patent/JPS5481738A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To prevent the malfunction caused by interruption, by suppressing the timing of interruption with a simple circuit constitution, through the provision of registers set with the logical product of reset signal and the setting of registers conditionally.
CONSTITUTION: In the interruption processing circuit in which the logical sum of the input signals A1 and A2 of a plurality is inputted to the microcomputer as the interruption signal, the reset signal of the logical sum is outputted from the response of the computer, and either of the input signal A1 or A2 is detected, the registers 201 and 202 set with the signal of the logical product between the input signal A1 or A2 and the logical sum of the response from computers are provided. Further, the logical product between the output of the registers 201 and 202 and the reset signal of response is inputted to the logical sum circuit 1 and the registers 201 and 202 are conditionally set by feeding back the NOT output of the registers 201 and 202 to the terminal P respectively. Further, the second and third interruption are inputted after the reset signal release at the reset signal output.
COPYRIGHT: (C)1979,JPO&Japio
JP15022377A 1977-12-13 1977-12-13 Multiplex interruption control circuit Pending JPS5481738A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15022377A JPS5481738A (en) 1977-12-13 1977-12-13 Multiplex interruption control circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15022377A JPS5481738A (en) 1977-12-13 1977-12-13 Multiplex interruption control circuit

Publications (1)

Publication Number Publication Date
JPS5481738A true JPS5481738A (en) 1979-06-29

Family

ID=15492218

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15022377A Pending JPS5481738A (en) 1977-12-13 1977-12-13 Multiplex interruption control circuit

Country Status (1)

Country Link
JP (1) JPS5481738A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5892024A (en) * 1981-11-17 1983-06-01 シ−メンス・アクチエンゲゼルシヤフト Control method and device for inter-system interface

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5062337A (en) * 1973-10-01 1975-05-28
JPS53131731A (en) * 1977-04-22 1978-11-16 Hitachi Ltd Interruption circuit for computer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5062337A (en) * 1973-10-01 1975-05-28
JPS53131731A (en) * 1977-04-22 1978-11-16 Hitachi Ltd Interruption circuit for computer

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5892024A (en) * 1981-11-17 1983-06-01 シ−メンス・アクチエンゲゼルシヤフト Control method and device for inter-system interface

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