JPS5484435A - Fault detecting method - Google Patents

Fault detecting method

Info

Publication number
JPS5484435A
JPS5484435A JP15176677A JP15176677A JPS5484435A JP S5484435 A JPS5484435 A JP S5484435A JP 15176677 A JP15176677 A JP 15176677A JP 15176677 A JP15176677 A JP 15176677A JP S5484435 A JPS5484435 A JP S5484435A
Authority
JP
Japan
Prior art keywords
signal
pwf
grown
address
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP15176677A
Other languages
Japanese (ja)
Other versions
JPS6148183B2 (en
Inventor
Hironari Okuno
Takashi Morikawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP15176677A priority Critical patent/JPS5484435A/en
Publication of JPS5484435A publication Critical patent/JPS5484435A/en
Publication of JPS6148183B2 publication Critical patent/JPS6148183B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Detection And Correction Of Errors (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To ensure an assured checking for the growing circuit and the like by securing the exclusive logical sum for the lowest rank bit signal of the start and end address signals and adding the grown signal as the parity signal of the grown partial writing signal.
CONSTITUTION: The fault is detected by address signal 1 showing the data start and address signal 3 showing the data end for PWF growing circuit 1 which produce the partial writing indication signal used when the data is written into the memory. In other words, the signal produced by securing exclusive logical sum 4 for the lowest rank bit signal of address signal 1 and 3 is added to in the form of the parity signal of grown partial writing signal PWF. Thus, an assured checking is ensured for the PWF growing circuit and the transmission line through a simple constitution.
COPYRIGHT: (C)1979,JPO&Japio
JP15176677A 1977-12-19 1977-12-19 Fault detecting method Granted JPS5484435A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15176677A JPS5484435A (en) 1977-12-19 1977-12-19 Fault detecting method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15176677A JPS5484435A (en) 1977-12-19 1977-12-19 Fault detecting method

Publications (2)

Publication Number Publication Date
JPS5484435A true JPS5484435A (en) 1979-07-05
JPS6148183B2 JPS6148183B2 (en) 1986-10-23

Family

ID=15525816

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15176677A Granted JPS5484435A (en) 1977-12-19 1977-12-19 Fault detecting method

Country Status (1)

Country Link
JP (1) JPS5484435A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1990002373A1 (en) * 1988-08-30 1990-03-08 Unisys Corporation Merge select decode checking

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6370987U (en) * 1986-10-29 1988-05-12
JPH0551085A (en) * 1991-08-15 1993-03-02 Suraidetsukusu Kk Storing case for information recording medium

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO1990002373A1 (en) * 1988-08-30 1990-03-08 Unisys Corporation Merge select decode checking

Also Published As

Publication number Publication date
JPS6148183B2 (en) 1986-10-23

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