JPS6148183B2 - - Google Patents
Info
- Publication number
- JPS6148183B2 JPS6148183B2 JP52151766A JP15176677A JPS6148183B2 JP S6148183 B2 JPS6148183 B2 JP S6148183B2 JP 52151766 A JP52151766 A JP 52151766A JP 15176677 A JP15176677 A JP 15176677A JP S6148183 B2 JPS6148183 B2 JP S6148183B2
- Authority
- JP
- Japan
- Prior art keywords
- pwf
- address
- data
- generation circuit
- partial write
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000001514 detection method Methods 0.000 claims 2
- 238000000034 method Methods 0.000 description 3
- 230000005540 biological transmission Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000008054 signal transmission Effects 0.000 description 1
Landscapes
- Techniques For Improving Reliability Of Storages (AREA)
- Detection And Correction Of Errors (AREA)
Description
本発明はメモリヘデータを書込む際に用いる部
分書込み指示信号（PWF）の発生回路の障害を
検出する方法に関する。
PWFがどのように用いられるかは周知であり
例えば特開昭49−120550号公報に開示されてい
る。従来は、PWF生成回路より出力されたPWF
自信からパリテイビツトを作成していた。これで
はPWF生成回路自身の障害の検出は不可能であ
る。
本発明の目的はPWF生成回路自身の障害を検
出する方法を提供することにある。
PWFが８ビツトすなわち１度にメモリに書込
むデータ量が８バイトである場合を例にとつて説
明する。図において信号A0〜A2は書込むべきデ
ータの始り地点を示す３ビツトのアドレス・信号
B0〜B2は終りの地点を示すやはり３ビツトのア
ドレスである。これ等の信号から生成される部分
書込み信号C0〜C7はPWF生成回路１によつて生
成される。８ビツトの部分書込み信号C0〜C7は
８バイトのデータの各バイトに１ビツトずつ対応
しており、A0〜A2が示す始まり地点からB0〜B2
が示す終りの地点までが連続して１にされる。例
えば、A0＝０，A1＝０，A2＝０，B0＝１，B1＝
１，B2＝１であればC0〜C7はすべて１であり、
A0＝０，A1＝１，A2＝１，B0＝１，B1＝１，B2
＝０であれば、C0＝０，C1＝０，C2＝０，C3＝
１，C4＝１，C5＝１，C6＝１，C7＝０となる。
PWF生成回路はA0〜A2，B0〜B2をデコードした
信号のAND，OR等の組合せ回路によつて実現で
きるが、この実現方法については、本発明と直接
関係しないので省略する。なお、A0〜A2，B0〜
B2には次の関係があることを前提とする。
（A0A1A2）2≦（B0B1B2）2ただし、〓２は２進数を
表す。
さてこのPWF生成回路及びPWF信号の伝送路
の障害を検出するために生成されたPWFC0〜C7
にパリテイビツトが付加される。このパリテイビ
ツトはA2とB2の排他的ORをとることによつて得
られる。なんとなれば、C0C1C2C3C4
C5C6C7＝A2B2の関係があるからである。
ここに、
C0＝0・1・2
C1＝0・1・0・1・2
C2＝0・（1＋2）・（B0＋B1）
C3＝0・（B0＋B1・B2）
C4＝（0＋1・2）・B0
C5＝（0＋1）・B0・（B1＋B2）
C6＝0・1・2・B0・B1
C7＝B0・B1・B2
The present invention relates to a method for detecting a failure in a circuit for generating a partial write instruction signal (PWF) used when writing data to a memory. How PWF is used is well known and is disclosed, for example, in Japanese Patent Application Laid-Open No. 120550/1983. Conventionally, the PWF output from the PWF generation circuit
I created Parity Bits out of confidence. In this case, it is impossible to detect a failure in the PWF generation circuit itself. An object of the present invention is to provide a method for detecting a failure in the PWF generation circuit itself. An example will be explained in which the PWF is 8 bits, that is, the amount of data written to the memory at one time is 8 bytes. In the figure, signals A 0 to A 2 are 3-bit address signals indicating the starting point of data to be written.
B0 to B2 are also 3-bit addresses indicating the end point. Partial write signals C 0 -C 7 generated from these signals are generated by the PWF generation circuit 1. The 8-bit partial write signals C 0 to C 7 correspond to one bit for each byte of the 8-byte data, and start from the starting point indicated by A 0 to A 2 to B 0 to B 2 .
is continuously set to 1 up to the end point indicated by . For example, A 0 =0, A 1 =0, A 2 =0, B 0 =1, B 1 =
1, if B 2 = 1, C 0 to C 7 are all 1,
A 0 = 0, A 1 = 1, A 2 = 1, B 0 = 1, B 1 = 1, B 2
= 0, C 0 = 0, C 1 = 0, C 2 = 0, C 3 =
1, C 4 =1, C 5 =1, C 6 =1, and C 7 =0.
The PWF generation circuit can be realized by a combination circuit such as AND or OR of signals obtained by decoding A 0 to A 2 and B 0 to B 2 , but the method for realizing this will be omitted since it is not directly related to the present invention. In addition, A 0 ~A 2 , B 0 ~
It is assumed that B 2 has the following relationship.
(A 0 A 1 A 2 ) 2 ≦ (B 0 B 1 B 2 ) 2However , 〓 2 represents a binary number. Now, this PWF generation circuit and PWFC 0 to C 7 generated to detect failures in the PWF signal transmission path.
A parity bit is added to This parity bit is obtained by exclusive ORing A 2 and B 2 . After all, C 0 C 1 C 2 C 3 C 4
This is because there is a relationship of C 5 C 6 C 7 = A 2 B 2 .
Here, C 0 = 0・1・2 C 1 = 0・1・0・1・2 C 2 = 0・( 1 + 2 )・(B 0 +B 1 ) C 3 = 0・(B 0 +B 1・B 2 ) C 4 = ( 0 + 1・2 )・B 0 C 5 = ( 0 + 1 )・B 0・(B 1 +B 2 ) C 6 = 0・1・2・B 0・B 1 C 7 = B0・B1・B2
【表】
このようにして発生されたC0〜Cpをパリテイ
チエツクすることにより、PWF生成回路ならび
に伝送路のチエツクが確実に、かつ簡単にでき
る。[Table] By checking the parity of C 0 to Cp generated in this manner, the PWF generation circuit and transmission line can be checked reliably and easily.
図は本発明の一実施例を示すブロツク図であ
る。
１…PWF生成回路、２…データ始点アドレス
信号、３…データ終点アドレス信号、４…排他的
OR回路、５…PWF転送線、６…PWFパリテ
イ。
The figure is a block diagram showing one embodiment of the present invention. 1...PWF generation circuit, 2...Data start point address signal, 3...Data end point address signal, 4...Exclusive
OR circuit, 5...PWF transfer line, 6...PWF parity.
Claims (1)
み指示信号を、データの始りを示すアドレスと終
りを示すアドレスから、作成する回路の障害を検
出するために、この始りアドレスと終りアドレス
の最下位のビツト信号の排他的論理和をとること
によつて作成された信号を、生成された部分書込
み指示信号のパリテイ信号として付加し、障害検
出を行なうことを特徴とする障害検出方法。1 A partial write instruction signal used when writing data to memory is created from an address indicating the start and an address indicating the end of the data.In order to detect a failure in the circuit, the last address of the start address and end address is A failure detection method characterized in that a signal created by taking the exclusive OR of lower bit signals is added as a parity signal to a generated partial write instruction signal to perform failure detection.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15176677A JPS5484435A (en) | 1977-12-19 | 1977-12-19 | Fault detecting method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15176677A JPS5484435A (en) | 1977-12-19 | 1977-12-19 | Fault detecting method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5484435A JPS5484435A (en) | 1979-07-05 |
| JPS6148183B2 true JPS6148183B2 (en) | 1986-10-23 |
Family
ID=15525816
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15176677A Granted JPS5484435A (en) | 1977-12-19 | 1977-12-19 | Fault detecting method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5484435A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6370987U (en) * | 1986-10-29 | 1988-05-12 | ||
| JPH0551085A (en) * | 1991-08-15 | 1993-03-02 | Suraidetsukusu Kk | Storing case for information recording medium |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| WO1990002373A1 (en) * | 1988-08-30 | 1990-03-08 | Unisys Corporation | Merge select decode checking |
-
1977
- 1977-12-19 JP JP15176677A patent/JPS5484435A/en active Granted
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6370987U (en) * | 1986-10-29 | 1988-05-12 | ||
| JPH0551085A (en) * | 1991-08-15 | 1993-03-02 | Suraidetsukusu Kk | Storing case for information recording medium |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS5484435A (en) | 1979-07-05 |
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