JPS5484471A - Anti-phase clock type ring counter - Google Patents
Anti-phase clock type ring counterInfo
- Publication number
- JPS5484471A JPS5484471A JP15263477A JP15263477A JPS5484471A JP S5484471 A JPS5484471 A JP S5484471A JP 15263477 A JP15263477 A JP 15263477A JP 15263477 A JP15263477 A JP 15263477A JP S5484471 A JPS5484471 A JP S5484471A
- Authority
- JP
- Japan
- Prior art keywords
- clock
- signal
- ring counter
- phase clock
- type ring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03K—PULSE TECHNIQUE
- H03K23/00—Pulse counters comprising counting chains; Frequency dividers comprising counting chains
- H03K23/40—Gating or clocking signals applied to all stages, i.e. synchronous counters
- H03K23/50—Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits
- H03K23/54—Ring counters, i.e. feedback shift register counters
Landscapes
- Manipulation Of Pulses (AREA)
Abstract
PURPOSE:To reduce the capacity of the clock oscillator circuit down to half as well as to sumplify the circuit constitution by changing the output of the clock oscillator circuit into the clock signals of different phases via the gate circuit. CONSTITUTION:Output signal CS of clock oscillator circuit 17 is delivered after conversion to clock signal CSb featuring the 180 deg. phase difference from clock signal CSa. And signal CSa is supplied to input terminal CK of FF11, 13 and 15 each, and signal CSb is supplied to terminal CK of FF12, 14 and 16 respectively. Thus, each clock signal makes FF11-16 function as the ring counter.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15263477A JPS5484471A (en) | 1977-12-19 | 1977-12-19 | Anti-phase clock type ring counter |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15263477A JPS5484471A (en) | 1977-12-19 | 1977-12-19 | Anti-phase clock type ring counter |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5484471A true JPS5484471A (en) | 1979-07-05 |
Family
ID=15544670
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15263477A Pending JPS5484471A (en) | 1977-12-19 | 1977-12-19 | Anti-phase clock type ring counter |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5484471A (en) |
Cited By (7)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62192097A (en) * | 1986-02-18 | 1987-08-22 | Nec Ic Microcomput Syst Ltd | Shift register circuit |
| JPS62192096A (en) * | 1986-02-18 | 1987-08-22 | Nec Ic Microcomput Syst Ltd | Shift register |
| JPH0341823A (en) * | 1989-07-07 | 1991-02-22 | Mitsubishi Electric Corp | Frequency divider |
| WO1998004042A1 (en) * | 1996-07-23 | 1998-01-29 | 3Com Ireland | Digital phase locked loop |
| EP0872959A1 (en) * | 1997-04-15 | 1998-10-21 | Koninklijke Philips Electronics N.V. | Low noise frequency divider |
| EP1293888A2 (en) | 2001-09-17 | 2003-03-19 | Broadcom Corporation | Methods and circuitry for implementing first-in first-out structure |
| JPWO2016027329A1 (en) * | 2014-08-20 | 2017-04-27 | 株式会社ソシオネクスト | Frequency divider and semiconductor integrated circuit |
-
1977
- 1977-12-19 JP JP15263477A patent/JPS5484471A/en active Pending
Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS62192097A (en) * | 1986-02-18 | 1987-08-22 | Nec Ic Microcomput Syst Ltd | Shift register circuit |
| JPS62192096A (en) * | 1986-02-18 | 1987-08-22 | Nec Ic Microcomput Syst Ltd | Shift register |
| JPH0341823A (en) * | 1989-07-07 | 1991-02-22 | Mitsubishi Electric Corp | Frequency divider |
| WO1998004042A1 (en) * | 1996-07-23 | 1998-01-29 | 3Com Ireland | Digital phase locked loop |
| GB2331192B (en) * | 1996-07-23 | 2001-03-07 | 3Com Ireland | Digital phase locked loop |
| GB2331192A (en) * | 1996-07-23 | 1999-05-12 | 3Com Ireland | Digital phase locked loop |
| US6163182A (en) * | 1997-04-15 | 2000-12-19 | U.S. Philips Corporation | Low-noise frequency divider |
| EP0872959A1 (en) * | 1997-04-15 | 1998-10-21 | Koninklijke Philips Electronics N.V. | Low noise frequency divider |
| EP1293888A2 (en) | 2001-09-17 | 2003-03-19 | Broadcom Corporation | Methods and circuitry for implementing first-in first-out structure |
| EP1293888A3 (en) * | 2001-09-17 | 2006-08-23 | Broadcom Corporation | Methods and circuitry for implementing first-in first-out structure |
| US7167024B2 (en) | 2001-09-17 | 2007-01-23 | Broadcom Corporation | Methods and circuitry for implementing first-in first-out structure |
| US7205792B2 (en) | 2001-09-17 | 2007-04-17 | Broadcom Corporation | Methods and circuitry for implementing first-in first-out structure |
| JPWO2016027329A1 (en) * | 2014-08-20 | 2017-04-27 | 株式会社ソシオネクスト | Frequency divider and semiconductor integrated circuit |
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