JPS5498546A - Test system for data processor - Google Patents

Test system for data processor

Info

Publication number
JPS5498546A
JPS5498546A JP598278A JP598278A JPS5498546A JP S5498546 A JPS5498546 A JP S5498546A JP 598278 A JP598278 A JP 598278A JP 598278 A JP598278 A JP 598278A JP S5498546 A JPS5498546 A JP S5498546A
Authority
JP
Japan
Prior art keywords
bus
output
instruction
input
register
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP598278A
Other languages
Japanese (ja)
Other versions
JPS619650B2 (en
Inventor
Mitsutoshi Nagoya
Junichi Iwasaki
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP598278A priority Critical patent/JPS5498546A/en
Publication of JPS5498546A publication Critical patent/JPS5498546A/en
Publication of JPS619650B2 publication Critical patent/JPS619650B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Executing Machine-Instructions (AREA)
  • Test And Diagnosis Of Digital Computers (AREA)
  • Microcomputers (AREA)

Abstract

PURPOSE: To reduce the semiconductor chip area, by utilizing the inner bus originally present in the central processor of one chip incorporating memory, and making unnecessary te exclusive bus through the connection of input and output port to this.
CONSTITUTION: The program instruction in the read only memory 11 constituting the central prcessor is given to the multiplexer 13 having the control input terminal 25 through the bus 12, and this output is set in the instruction register 15 via the bus 14. Next, this instruction is added with the decoder 17 through the bus 16 where it is interpreted, and it is outputted to the output port 19 via the internal bus 18 or is fetched in the bus 18 as data through the input port 21. In testing the unit of this constitution, the input and output port 23 is connected to the bus 18 and the bus 18 is connected to the input side of the multiplexer 13 via the bus 31. Further, the output bus 16 of the register 15 is connected to the bus 18 through the bus 32 and the content of the register 15 is fed to the bus 18. Thus, the buses for exclusive use of instruction and output are made unnecessary.
COPYRIGHT: (C)1979,JPO&Japio
JP598278A 1978-01-23 1978-01-23 Test system for data processor Granted JPS5498546A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP598278A JPS5498546A (en) 1978-01-23 1978-01-23 Test system for data processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP598278A JPS5498546A (en) 1978-01-23 1978-01-23 Test system for data processor

Related Child Applications (1)

Application Number Title Priority Date Filing Date
JP60208189A Division JPS6168647A (en) 1985-09-20 1985-09-20 Data processing device

Publications (2)

Publication Number Publication Date
JPS5498546A true JPS5498546A (en) 1979-08-03
JPS619650B2 JPS619650B2 (en) 1986-03-25

Family

ID=11626014

Family Applications (1)

Application Number Title Priority Date Filing Date
JP598278A Granted JPS5498546A (en) 1978-01-23 1978-01-23 Test system for data processor

Country Status (1)

Country Link
JP (1) JPS5498546A (en)

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56152058A (en) * 1980-04-25 1981-11-25 Matsushita Electric Ind Co Ltd Test system for chip of one-chip microcomputer
JPS5897731A (en) * 1981-12-07 1983-06-10 Hitachi Ltd I/O control method for logic integrated circuits
JPS61128343A (en) * 1984-11-28 1986-06-16 Nec Corp Microcomputer device
JPH01116860A (en) * 1987-10-30 1989-05-09 Yokogawa Hewlett Packard Ltd Microprocessor

Cited By (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56152058A (en) * 1980-04-25 1981-11-25 Matsushita Electric Ind Co Ltd Test system for chip of one-chip microcomputer
JPS5897731A (en) * 1981-12-07 1983-06-10 Hitachi Ltd I/O control method for logic integrated circuits
JPS61128343A (en) * 1984-11-28 1986-06-16 Nec Corp Microcomputer device
JPH01116860A (en) * 1987-10-30 1989-05-09 Yokogawa Hewlett Packard Ltd Microprocessor

Also Published As

Publication number Publication date
JPS619650B2 (en) 1986-03-25

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