JPS5897731A - I/O control method for logic integrated circuits - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to an input/output control method for logic integrated circuits, and in particular, in large-scale integrated circuits using a precharge type data bus, data transfer is performed asynchronously with an external device. This will lead to improved input/output control methods.

As mital commiscators have recently come into wide use in various applications, it has become necessary to connect other processing devices and microcomputers to mutually transfer data. Furthermore, recent microcomputers use a circuit configuration in which the data bus is precharged during a portion of one machine cycle in order to operate at high speed. , transfer input and output data via the data bus.

Conventionally, such a microcomputer llf) 1ml
In physical integrated circuits, when data is transferred between an interconnected external device and an internal register, a method is adopted in which the internal register and external device register are synchronized, or a precharge method is used. ``The C-insert data bus's circuit configuration is clearly reflected in the way it is implemented.

However, the former method requires complex synchronization circuits to transfer data between multiple devices with different clocks, and the latter method requires internal registers and internal path interface circuits. It becomes complicated.

An object of the present invention, in order to eliminate such conventional drawbacks, is to perform high-speed operation using a precharge-type data path configuration, and to provide a high-speed operation between an internal register and an external device that operates using a different system of clocks. This allows data transfer with almost no increase in circuit scale. An object of the present invention is to provide an input/output control method for a logic integrated circuit that can perform the following steps.

In order to achieve the above object, the logic integrated circuit input/output control method according to the present invention uses MOS (Mstaj 0xIL
s8/m1eon (modified ultor)), which transfers data between memory, registers, arithmetic circuits, etc. after precharging the internal data bus, the logic integrated circuit uses a black clock. When an operating external device asynchronously requests data transfer to a data register in the logic integrated circuit via the internal data bus, the logic integrated circuit's operating clock is temporarily stopped and the internal data bus is switched off. It is characterized in that it is connected in circuitry to an external device and further precharges the internal data bus with a signal that occurs during the initial period of a data transfer cycle.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an MO8 digital large-scale integrated circuit to which the present invention is applied.

In Figure 1, an MO8 digital large-scale integrated circuit (
1 (hereinafter referred to as LSI) 1 and a device (for example, 1 digital computer) 2 that is connected to it and performs data transfer are shown, and LS11 and digital computer 2 each operate at an asynchronous frequency and jitter. It is assumed that there is

Lgll includes an arithmetic circuit (ALU) 10, a data storage device (RAM) 11, and multiple data registers (]LItG
1, 2) 12.13% A memory device (ROM) 14 storing a program that controls internal operations, an input/output circuit (input/output circuit) 15 that is an interface with an external digital computer, and timing control. A circuit (control) 16 is provided.

The LSII and the digital computer 2 have an n-bit data bus 3, an m-bit function bus 5, a chip select signal (O8) 6, and a read/write control signal (
R/W) 7, and data transfer timing signal (II:
)8 is connected.

Figure 2 shows the bus used inside the LSI in Figure 1.
3 is a configuration diagram of a data transfer circuit using a precharge method, and FIG. 3 is an operation time chart of FIG. 2.

As shown in FIG. 2, a commonly used data transfer circuit using a bus precharge method for high-speed operation in MOS-L8I includes a transistor T for precharging the data path D1.

Switch transistor Tl r Tl , one switch control register, register 1 for setting transfer data
Consists of 8 mag. In addition, A is a control signal for precharging the bus, B is an output signal of the register 17, and C is a control signal for precharging the bus.
E is a control signal that gives the timing to output the contents of the register 17 to the bus, a data bus indicating one of several DFimI buses, and E is a control signal that takes the contents of the bus into the register 18.

The LaI3 operates in a constant cycle ('l'cyo) as shown in FIG. In this cycle,
First, the parasitic capacitance jlC1 of the data bus D is precharged by the signal generator through the transistor T (see FIG. 3). As a result, the logic level of the data bus DFi becomes "which state (see Figure 3). After the precharging is completed, the output B of the register 17 is outputted to the data bus D by the signal C (see Figure 3). , C). At this time,
If the content of the register 17 is "1", the transistor T is turned on, the charge of the parasitic capacitance C1 is discharged through the transistor T11T, and the data bus D becomes "0" ( (See the low level in the third diagram).On the other hand, if the output B of the register 17 is 0, the transistor is '1'.
No current flows through T, and the data bus DFi is kept in the "1" state (see the high level in the third diagram).

The state of data bus D is set by timing bus E through inverter Gl in register 18.

FIG. 4 is a configuration diagram of a data transfer control circuit in an LSI showing an embodiment of the present invention, and FIGS. 5 and 6 are operation time charts in FIG. 4.

The data bus 3.4 in FIG. 4 is an n-bit network. In addition to the circuit shown in 1F,
A clock generation circuit 19 and an internal control timing generation circuit 20 that generate control timing are shown. φ
. , φ0. φ, , φ are the basic four-phase overlap Vts that control each part within the LSI 1. Signals A, C, Ea in FIG. 3, and signal 3 in FIG. 4, respectively.
0.34-. 33, and in FIG. 4, there are also input/output signals (control signal 35 of the 7A 15, signal DIalt indicating the stop of internal normal operation) 31, and internal registers 21 and 22 of the L12 811 from the outside. A signal (Hazt-D) 32 is shown requesting data transfer.

tIv, Figure 5 shows the timing during normal operation, and the sixth
The figure shows the timing of register data read operation when there is an external data transfer request.

In FIG. 6, the chip for selecting LSI1 is
Since the select signal F is inputted to 1%/', a four-phase p-twinter φ is generated by the chic generator 19 as shown in FIG. ~φ, and L s l
The internal circuit of l operates.

a precharge signal 30 corresponding to the signal person C21;
The data output signal 34 and the data input signal 33 are basically outputted by the internal control timing generation circuit 20 shown in FIG.

It is generated by combining and subsuming ~φ. In this state, the input/output control signal 35, data transfer request signal (Bazt-D) 32, and operation stop signal (Hajt-D) are activated.
)31 signals are generated fkvh.

On the other hand, when there is a data transfer request from an external digital computer, when the transfer request (hood is given by the 7 action signal 6 and the 1 chip select signal 7 is input as shown in FIG. 6 (6), The control circuit 16 shown in FIG. 4 detects this and sends a data transfer request signal 32 to the ripple clock generator 19. This causes the ripple clock generator 19 to send a signal indicating that normal operation is to be stopped. (](ajt-D) 31 is output.

At the occurrence of rip-lock rr19, the clock φ. ~φ, is delayed for 1/8 cycles, and the stop signal "[1(act
) 31 (see FIG. 6(t)). During this A cycle, a precharge signal 30 is outputted by a circuit Fi different from that in normal times, and the data bus 4 is precharged to the level "1" (see FIG. 6, 6II, (n)).

Data output signal 3 is generated by external timing signal 6.
4 is generated from an internal control timing generation circuit 20.

The data output signal 34 is connected to the transistor T.
Turn on registers 21 to 221-1 m
-n is output to the data path through transistors 'r, -1 to Ts-0 (see operation in FIGS. 2 and 3). The content of the data bus only is the timing signal 6.
LSI with I10 control signal 3δ controlled by
It is output to the external data bus 3 of I and read out to the digital computer 2.

When one data transfer is completed, the chip select signal 7 disappears, so this is sent to the control circuit 1 in Figure 4.
6 and the basic clock φ is detected again.

~φ, and enters normal operation.

Figure 7 shows the basic ivy (φ, ~φ,) in Figure 4.
, precharge signal 30 and operation stop signal (Hajt
) is a configuration diagram of a circuit that generates 31.

The four-phase clock generator 19 receives a single-phase input clock (OL
K2) generates four-phase overlap clocks (φ., φ8.φ□, φ1.) shown in FIG. 6-) to O).

When data transfer request signal (Hajt-D) 32 is input, φ1.・φ
At the timing of □, do 79 knobs and 70 knobs 24). Next, φ8. At the timing of 7 rip, 7a flip 23
is set, and the set output signal and the 41H overlap data block (≠.r-IIg) are connected to a NAND gate (0
3~G6) and enter the basic Yushitsutana. ~φ, stops outputting. On the other hand, when the 7-rip/7-w block 24 is set, an AND signal with the cyclic clock φ From '['cy
Set the 7 lip-flop 25 with a delay of c/5. The Q output of the flip flip 25 becomes a stop signal (HlLlt) 31, and is ANDed with the Q output of the flip 70 tube 23 in a NAND gate G8 to control the data bus pre-load during data transfer with the outside. A charge signal 30 is output (see FIG. 6-) (b)).

When the data transfer request signal (Hajt-D) 32 becomes "0", the flip-flops 24-. 23 is reset at each timing, and the basic clock φ is generated from NAND G6)03 to G6. ~φ is output again, and 7 rip.
The output of the 7-bit flip 24 and the clocks φ and y are ANDed by a NAND gate G11, and inputted to the terminal of the flip 70-tube 25 to reset it.

The stop signal (Ha7t) 31 becomes "0" and returns to the normal operating state.

In addition, in Fig. 6-), the bus precharge signal 30 (shown with diagonal lines) generated during data transfer between the cabinet and the outside is the bus precharge signal 3 generated during normal operation.
It happens to occur at the same time as 0, but it goes without saying that it would be difficult to cause it to occur at an arbitrary different time.

As explained above, according to the present invention, when high-speed operation is performed using a precharge type data bus configuration in a large-scale integrated circuit configured with Mo2, an external register can be accessed from an internal register. If a data transfer request is made, the internal tarotutter operation mode is stopped, and a bus precharge signal is generated independently during data transfer with the outside, so each bit of multiple internal registers is There is no need to add a circuit for each integrated circuit, and data can be transferred to and from the outside while minimizing the increase in the circuit scale of the integrated circuit.

[Brief explanation of drawings]

Fig. 1 is a block diagram of a splitter of a logic integrated circuit which is the subject of the present invention; Fig. 2 is a block diagram of a bus precharge type data transfer circuit used in the circuit of Fig. 1;
FIG. 4 is a configuration diagram of a data transfer control section in a logic integrated circuit showing an embodiment of the present invention, and FIGS. 6 and 6 are operation time charts in FIG. 4, respectively. , FIG. 7 is a block diagram of a circuit that generates a clock, a precharge signal, a stop signal, etc. in FIG. 4. 1: Logic integrated circuit (Lsz), 2: External device (digital calculation lIb4), 3 = External data bus, '4 = Internal data bus, 19: 4x generation circuit, 20: Internal division timing generation circuit , 17, 18° 21.22: Register, 23t24.25: Flip 70 knob. 11th CLKI CLK2 2nd
Figure 3 E'l ■ Figure 4 LK2 Figure 5 Figure 6 Figure 7 Continued from page 1 Applicant Hitachi Electronics Co., Ltd. 1-23-2 Kanda Suda-cho, Chiyoda-ku, Tokyo

Claims (1)

[Claims] M O8 (M@taJ Qxlds ll*m1oon
In a logic integrated circuit that is configured with an auator and that precharges an internal data bus and then transfers data using jumps such as memory, arithmetic circuits, registers, etc., an external device that operates on a different clock than the logic integrated circuit If there is an asynchronous data transfer request to the data register in the logic integrated circuit via the internal data bus, the internal critter of the logic integrated circuit is temporarily stopped and the internal data bus is transferred to the external device. An input/output control method for a logic integrated circuit, which is connected in a circuit and further precharges an internal data bus by an external control signal whose internal clock is lII& during the first period of a data transfer cycle. .