JPS55105342A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE: To reduce a gate-drain capacity and to improve a power-time product by providing V-shaped concave portions having different depths in a separating region, in a taking-out region, and a gate region of electrostatic-induction transistor.

CONSTITUTION: An N⁺-embeded region 17 is diffused and formed on a P-type semiconductor substrate 19, and N-layer 16 is epitaxially grown all over the surface including the region 17. Then, a V-shaped concave separating groove 21 which is located between both sides of the region 17 and enters into the substrate 19, and a V-shaped concave electrode-taking-out grooves 22 which pierces through the region 17 and reaches the inside of the substrate 19 are formed by anisotropic etching. Furthermore, a V-shaped concave groove 23 is provided in the island-shaped layer 16, an N-type drain region 14 is diffused and formed on the flat-top portion of the island-shaped layer 16, and a P-type gate region 13 is diffused and formed at the bottom of the groove 23. A P-type separating layer is provided on the side walls and the bottom of the groove 21, and all the surface is protected by an oxide film 18. In this constitution, an electrostatic induction transistor having excellent power- delay-time product characteristics can be obtained.

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