JPS55112092A - Subscriber circuit - Google Patents

Subscriber circuit

Info

Publication number
JPS55112092A
JPS55112092A JP2044279A JP2044279A JPS55112092A JP S55112092 A JPS55112092 A JP S55112092A JP 2044279 A JP2044279 A JP 2044279A JP 2044279 A JP2044279 A JP 2044279A JP S55112092 A JPS55112092 A JP S55112092A
Authority
JP
Japan
Prior art keywords
capacitor
terminals
exchange
voltage
fet21
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP2044279A
Other languages
Japanese (ja)
Inventor
Toshihisa Yoshida
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP2044279A priority Critical patent/JPS55112092A/en
Publication of JPS55112092A publication Critical patent/JPS55112092A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04Q—SELECTING
    • H04Q3/00—Selecting arrangements

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Interface Circuits In Exchanges (AREA)

Abstract

PURPOSE:To supply the low-level signal to the side of the exchange by connecting the capacitor between the channels which are between the exchange and the subscriber telephone and then sampling the signals of the capacitor along with the conversion given to the DC level. CONSTITUTION:The subscriber telephone is connected to terminals 10 and 11 each; while the exchange is conncted to terminals 28 and 29 each. On the other hand, the subscriber circuit consists of FET21, 22, 23 and 24, capacitor 25 plus gate pulse circuit 27 each. The potential difference between the collectors of transistors 14 and 15 is sampled by FET21 and 22 to be then held at capacitor 25. And the signals between terminals 28 and 29 are sampled by FET23 and 24. The voltage emerging between terminals 28 and 29 becomes identical to that obtained by subtracting the voltage set by resistance 26 from the voltage held at capacitor 25. Thus the low-level signal can be supplied to the side of the exchange.
JP2044279A 1979-02-22 1979-02-22 Subscriber circuit Pending JPS55112092A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP2044279A JPS55112092A (en) 1979-02-22 1979-02-22 Subscriber circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2044279A JPS55112092A (en) 1979-02-22 1979-02-22 Subscriber circuit

Publications (1)

Publication Number Publication Date
JPS55112092A true JPS55112092A (en) 1980-08-29

Family

ID=12027154

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2044279A Pending JPS55112092A (en) 1979-02-22 1979-02-22 Subscriber circuit

Country Status (1)

Country Link
JP (1) JPS55112092A (en)

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