JPS551160A - Current mirror circuit - Google Patents

Current mirror circuit

Info

Publication number
JPS551160A
JPS551160A JP14789278A JP14789278A JPS551160A JP S551160 A JPS551160 A JP S551160A JP 14789278 A JP14789278 A JP 14789278A JP 14789278 A JP14789278 A JP 14789278A JP S551160 A JPS551160 A JP S551160A
Authority
JP
Japan
Prior art keywords
mirror circuit
injector
current
current mirror
broken line
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP14789278A
Other languages
Japanese (ja)
Inventor
Yutaka Okada
Toru Nakamura
Takahiro Okabe
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP14789278A priority Critical patent/JPS551160A/en
Publication of JPS551160A publication Critical patent/JPS551160A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/65—Integrated injection logic

Landscapes

  • Amplifiers (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To use an I<2>L as a load of a current mirror circuit consisting of PNP (NPN) transistors, its injector being common to the I<2>L of other group, and to derive a specific current from the transistors of the mirror circuit thereby to unnecessitate the pinch resistor. CONSTITUTION:The broken line part 40 designates a logical circuit constituted by the I<2>L, and an injector current Iinj is caused to flow from a source Vcc through a resistor Rc to a common injector line 32. The broken line part 30 designates a load part of the current mirror circuit, and constitutes the current mirror circuit together with the broken line part 20. In this mirror circuit there is provided I<2>L consisting of a lateral PNP element 204 and a vertical inversed NPN element 203, and the injector is used as an I<2>L logical circuit. The output of one 36 of multicollectors of the element 203 is connected to the base, and the base terminal 33 is opened to cause a current to flow through an injector terminal 31. In this manner, the pinch resistor is substituted for one step part of the I<2>L gate to miniaturize the device.
JP14789278A 1978-12-01 1978-12-01 Current mirror circuit Pending JPS551160A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14789278A JPS551160A (en) 1978-12-01 1978-12-01 Current mirror circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14789278A JPS551160A (en) 1978-12-01 1978-12-01 Current mirror circuit

Publications (1)

Publication Number Publication Date
JPS551160A true JPS551160A (en) 1980-01-07

Family

ID=15440528

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14789278A Pending JPS551160A (en) 1978-12-01 1978-12-01 Current mirror circuit

Country Status (1)

Country Link
JP (1) JPS551160A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56164632A (en) * 1980-05-22 1981-12-17 Nec Corp Interface circuit using integrated injection type logical element

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS503756A (en) * 1973-04-13 1975-01-16
JPS5216157A (en) * 1975-07-28 1977-02-07 Nippon Telegr & Teleph Corp <Ntt> Integrated semiconductor logical circuit

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS503756A (en) * 1973-04-13 1975-01-16
JPS5216157A (en) * 1975-07-28 1977-02-07 Nippon Telegr & Teleph Corp <Ntt> Integrated semiconductor logical circuit

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS56164632A (en) * 1980-05-22 1981-12-17 Nec Corp Interface circuit using integrated injection type logical element

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