JPS55116151A - Automatic generation system for stepwise advance number of clocks - Google Patents

Automatic generation system for stepwise advance number of clocks

Info

Publication number
JPS55116151A
JPS55116151A JP2425979A JP2425979A JPS55116151A JP S55116151 A JPS55116151 A JP S55116151A JP 2425979 A JP2425979 A JP 2425979A JP 2425979 A JP2425979 A JP 2425979A JP S55116151 A JPS55116151 A JP S55116151A
Authority
JP
Japan
Prior art keywords
clocks
stepwise
advance number
scan
counter
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2425979A
Other languages
Japanese (ja)
Other versions
JPS594052B2 (en
Inventor
Tadakatsu Yoshikawa
Shigehito Mori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
NTT Inc
Original Assignee
Fujitsu Ltd
Nippon Telegraph and Telephone Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd, Nippon Telegraph and Telephone Corp filed Critical Fujitsu Ltd
Priority to JP54024259A priority Critical patent/JPS594052B2/en
Publication of JPS55116151A publication Critical patent/JPS55116151A/en
Publication of JPS594052B2 publication Critical patent/JPS594052B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Test And Diagnosis Of Digital Computers (AREA)

Abstract

PURPOSE: To make it possible to generate automatically the stepwise advance number of clocks by advancing clocks stepwise by applying a fixed test input to a normal unit to be diagnosed, and then by finding the stepwise advance number of clocks when the unit comes in a fixed state.
CONSTITUTION: Counter 9 of controller 5 is reset and a test input is applied to normal processor 4. A scan-out address from unit 4 is set in scan-out address stack 10 and the fixed comparison value of a signal group is also set in register 6; and an advance of one clock is made to set counter 9 to "+1". On the basis of the scan-out address of stack 10, states are read out in sequence and set sequentially in register 7; and comparator circuit 8 makes a comparison between the contents of registers 6 and 7 and until the both agree, this processing is repeated, so that when the both agree each other, the content of counter 9 at that time will be read out. Consequently, the stepwise advance number of clocks can automatically be found and diagnostic data for a function diagnosis can be generated efficiently and accurately.
COPYRIGHT: (C)1980,JPO&Japio
JP54024259A 1979-03-02 1979-03-02 Clock step number automatic creation method Expired JPS594052B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54024259A JPS594052B2 (en) 1979-03-02 1979-03-02 Clock step number automatic creation method

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54024259A JPS594052B2 (en) 1979-03-02 1979-03-02 Clock step number automatic creation method

Publications (2)

Publication Number Publication Date
JPS55116151A true JPS55116151A (en) 1980-09-06
JPS594052B2 JPS594052B2 (en) 1984-01-27

Family

ID=12133231

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54024259A Expired JPS594052B2 (en) 1979-03-02 1979-03-02 Clock step number automatic creation method

Country Status (1)

Country Link
JP (1) JPS594052B2 (en)

Also Published As

Publication number Publication date
JPS594052B2 (en) 1984-01-27

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