JPS551181A - Method of producing complementary mis integrated circuit apparatus - Google Patents

Method of producing complementary mis integrated circuit apparatus

Info

Publication number
JPS551181A
JPS551181A JP4535779A JP4535779A JPS551181A JP S551181 A JPS551181 A JP S551181A JP 4535779 A JP4535779 A JP 4535779A JP 4535779 A JP4535779 A JP 4535779A JP S551181 A JPS551181 A JP S551181A
Authority
JP
Japan
Prior art keywords
section
film
oxide film
polycrystal
source
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4535779A
Other languages
Japanese (ja)
Other versions
JPS5829626B2 (en
Inventor
Kazuo Yudasaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP54045357A priority Critical patent/JPS5829626B2/en
Publication of JPS551181A publication Critical patent/JPS551181A/en
Publication of JPS5829626B2 publication Critical patent/JPS5829626B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To produce a MISIC containing a thin film resistor made of a polycrystal Si by setting the polycrystal at a desired resistance value by a impurity ion implantation method. CONSTITUTION:An oxide film is formed on a n-type Si substrate 1 on which a p well region and a polycrystal Si layer 8 is formed on an oxide film 7 made at the formation of the well. Then, all parts are removed only leaving the gate and the portions 8a to 8c serving as the variable resistance section. An ion implantation is conducted at the variable resistance section 8c to obtain the desired resistance value. The oxide films 7a and 7c is removed with portion corresponding to the source and drain and well regions 23 with the portions 8a to 8c as a mask. Then, an oxide film 9 is applied and the film is removed in the portion corresponding to the p-channel MOSFET forming section. The source, drain regions 10 and 11, a electrode withdrawing section 24, and the both ends 8c1 to 8c2 of the resistance section 8c are transformed to a p-type high density impurity region. Then, after the removal of the film, an oxide film 13 is formed. The film is removed from the n-channel MOSFET section and source and drain regions 14 and 15 are formed to make the gate electrode section 8a a n<+> type.
JP54045357A 1979-04-16 1979-04-16 Method for manufacturing complementary MIS integrated circuit device Expired JPS5829626B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54045357A JPS5829626B2 (en) 1979-04-16 1979-04-16 Method for manufacturing complementary MIS integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54045357A JPS5829626B2 (en) 1979-04-16 1979-04-16 Method for manufacturing complementary MIS integrated circuit device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP11582373A Division JPS5321992B2 (en) 1973-10-17 1973-10-17

Publications (2)

Publication Number Publication Date
JPS551181A true JPS551181A (en) 1980-01-07
JPS5829626B2 JPS5829626B2 (en) 1983-06-23

Family

ID=12717024

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54045357A Expired JPS5829626B2 (en) 1979-04-16 1979-04-16 Method for manufacturing complementary MIS integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5829626B2 (en)

Also Published As

Publication number Publication date
JPS5829626B2 (en) 1983-06-23

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