JPS551180A - Method of producing mis integrated circuit apparatus - Google Patents

Method of producing mis integrated circuit apparatus

Info

Publication number
JPS551180A
JPS551180A JP4535679A JP4535679A JPS551180A JP S551180 A JPS551180 A JP S551180A JP 4535679 A JP4535679 A JP 4535679A JP 4535679 A JP4535679 A JP 4535679A JP S551180 A JPS551180 A JP S551180A
Authority
JP
Japan
Prior art keywords
section
film
polycrystal
drain regions
portion corresponding
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4535679A
Other languages
Japanese (ja)
Other versions
JPS5829625B2 (en
Inventor
Kazuo Yudasaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP54045356A priority Critical patent/JPS5829625B2/en
Publication of JPS551180A publication Critical patent/JPS551180A/en
Publication of JPS5829625B2 publication Critical patent/JPS5829625B2/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To produce a MISIC containing a thin film resistor made of a polycrystal Si by setting the polycrystal at a desired resistance value by an impurity ion implantation method. CONSTITUTION:A polycrystal Si layer 8 is formed on oxide film 5 and 7 on a n-type Si substrate 1 on which a p well region is formed. Then, all parts are removed only leaving the gate and the portions 8a to 8c serving as the variable resistance section. Then an ion implantation is conducted at the variable resistance section 8c to obtain a desired resistance value. Then, the oxide films 7 and 7' are removed in the portion corresponding to the source and drain regions with the portions 8a and 8b as a mask. An oxide film 9 is applied on the surface of the substrate 1 and the film 9 is removed in the portion corresponding to the p channel MOSFET forming section is removed. With the diffusion, the source and drain regions 10 and 11 and the both ends of the resistance section 8c are transformed to a p-type high density impurity region. Then, after the removal of the film 9, an oxide film 13 is formed and then, the film 13 is removed in the portion corresponding to the n-channel MOSFET forming one section. Subsequently, source and drain regions 14 and 15 are formed to make the gate electrode section 8a a n-type.
JP54045356A 1979-04-16 1979-04-16 Manufacturing method for MIS integrated circuit device Expired JPS5829625B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54045356A JPS5829625B2 (en) 1979-04-16 1979-04-16 Manufacturing method for MIS integrated circuit device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54045356A JPS5829625B2 (en) 1979-04-16 1979-04-16 Manufacturing method for MIS integrated circuit device

Related Parent Applications (1)

Application Number Title Priority Date Filing Date
JP11582373A Division JPS5321992B2 (en) 1973-10-17 1973-10-17

Publications (2)

Publication Number Publication Date
JPS551180A true JPS551180A (en) 1980-01-07
JPS5829625B2 JPS5829625B2 (en) 1983-06-23

Family

ID=12716994

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54045356A Expired JPS5829625B2 (en) 1979-04-16 1979-04-16 Manufacturing method for MIS integrated circuit device

Country Status (1)

Country Link
JP (1) JPS5829625B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5878740A (en) * 1981-11-02 1983-05-12 Sumitomo Rubber Ind Ltd Method and apparatus for manufacturing tire

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5878740A (en) * 1981-11-02 1983-05-12 Sumitomo Rubber Ind Ltd Method and apparatus for manufacturing tire

Also Published As

Publication number Publication date
JPS5829625B2 (en) 1983-06-23

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