JPS55123748A - Data processing unit having latch circuit part - Google Patents

Data processing unit having latch circuit part

Info

Publication number
JPS55123748A
JPS55123748A JP3029279A JP3029279A JPS55123748A JP S55123748 A JPS55123748 A JP S55123748A JP 3029279 A JP3029279 A JP 3029279A JP 3029279 A JP3029279 A JP 3029279A JP S55123748 A JPS55123748 A JP S55123748A
Authority
JP
Japan
Prior art keywords
output
state
wired
latch circuit
data processing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP3029279A
Other languages
Japanese (ja)
Other versions
JPS6030971B2 (en
Inventor
Takeshi Murata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP54030292A priority Critical patent/JPS6030971B2/en
Publication of JPS55123748A publication Critical patent/JPS55123748A/en
Publication of JPS6030971B2 publication Critical patent/JPS6030971B2/en
Expired legal-status Critical Current

Links

Landscapes

  • Executing Machine-Instructions (AREA)
  • Logic Circuits (AREA)

Abstract

PURPOSE: To use a tri-state output element to obtain a wired OR connectable latch circuit, by wired-OR-connecting the output of the bit correspondene unit of a latch circuit to the bit output corresponding to the output of a data processing unit.
CONSTITUTION: Data processing part 1 performs operations and holding of given data, and output data of processing part 1 is latched in 6, and data processing part 5 connects the output from latch circuit 6 and the wired OR logic. Here, circuit 6 is so constituted that conversion to the turning-on state or the turning-off state of gate 8-1 may be rapider than conversion to the turning-off state or the turning-on state of gate 9-1 at the rise time or the fall time of a clock signal. The output of the bit correspondence unit of circuit 6 is wired-OR-connected to the bit output corresponding to output data of processing part 5. As a result, a tri-state output element can be used to obtain wired OR connectable circuit 6.
COPYRIGHT: (C)1980,JPO&Japio
JP54030292A 1979-03-15 1979-03-15 Data processing device with latch circuit section Expired JPS6030971B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP54030292A JPS6030971B2 (en) 1979-03-15 1979-03-15 Data processing device with latch circuit section

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP54030292A JPS6030971B2 (en) 1979-03-15 1979-03-15 Data processing device with latch circuit section

Publications (2)

Publication Number Publication Date
JPS55123748A true JPS55123748A (en) 1980-09-24
JPS6030971B2 JPS6030971B2 (en) 1985-07-19

Family

ID=12299645

Family Applications (1)

Application Number Title Priority Date Filing Date
JP54030292A Expired JPS6030971B2 (en) 1979-03-15 1979-03-15 Data processing device with latch circuit section

Country Status (1)

Country Link
JP (1) JPS6030971B2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04260957A (en) * 1990-09-03 1992-09-16 Internatl Business Mach Corp <Ibm> Computer system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH04260957A (en) * 1990-09-03 1992-09-16 Internatl Business Mach Corp <Ibm> Computer system

Also Published As

Publication number Publication date
JPS6030971B2 (en) 1985-07-19

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