JPS6030971B2 - Data processing device with latch circuit section - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention provides a data processing device having a latch circuit section, in particular, a latch circuit section which is a variable-or circuit using a circuit section having a tri-state output element and capable of variable-OR, For example, the present invention relates to a data processing device having a latch circuit section used in a processing section that latches extracted data from a local storage or latches output data from an arithmetic unit.

Although the present invention is not limited thereto, in recent years, high-speed, high-density, and inexpensive memory elements have been developed, and various registers inside a central processing unit are configured using the above-mentioned memory elements.・It is starting to be replaced by storage.

like this. On the output side of the local storage, {iW
A latch circuit or a A register circuit can be created. FIG. 1 and FIG. 2 each show an embodiment in which a latch circuit and a register circuit are used for the output of local storage.

In the figure, 1 is local storage, 2 is arithmetic unit,
3 is an A register, 4 is a B register, 5 is a C register, etc. corresponding to the second data processing section according to the present invention;
Reference numeral 6 represents a latch circuit section, 7 an OR logic section, and 8 an address conversion circuit section. In the case shown in Figure 1, the local
The data retrieved from the storage 1 is set in the register 4 for one day, is operated on the contents of the register 3 through the arithmetic unit 2, and is stored in the local storage 1, for example.

In this case, two machine cycles are required for one arithmetic processing, and when the second data processing section is capable of directly outputting data like the register 5 shown in the figure, and when performing an arithmetic operation using the contents of the register 5, This method has the disadvantage of causing wasted time. In the case shown in FIG. 2, data read from the local storage 1 is latched by the latch circuit section 6, operated on the contents of the register 3, and stored in, for example, the local storage 11.

In this case, since the data latched by the latch circuit section 6 is supplied to the arithmetic unit 2 as is, one machine
It can be executed in cycles. Furthermore, even when executing in the machine cycle, there is still time to operate the contents of register 5. Therefore, for example, when converting a calculation result into access address information for the main memory, it is possible to have the address conversion circuit 8 perform the address conversion within one machine cycle. Second
In order to obtain the circuit configuration shown in the figure, it is desirable to simply use OR logic, but in recent years, a TTLIC that can be wired-OR coupled using tri-state output elements has been developed, and the conventional open-collector type TTLIC has been developed. It has the characteristic of being faster than a wired-or join.

SUMMARY OF THE INVENTION An object of the present invention is to provide a data processing device in which the latch circuit used in the circuit configuration shown in FIG. 2 is composed of tri-state output elements. Therefore, a data processing device having a latch circuit section according to the present invention includes a first data processing section having a function of calculating and/or holding given data, and a latch circuit that latches output data from the data processing section. and a second data processing section whose output is coupled with the output from the latch circuit section by wire-or logic,
Data having a latch circuit section that extracts latch output data obtained by latching the output data of the data processing section of the data processing section by the latch circuit section and output data corresponding to the output data of the second data processing section using the wired-OR logic. In the processing device, the latch circuit section includes, in each bit corresponding unit, a tri-state output element whose output is controlled by an output control signal and has an OR function for at least two inputs, and a tri-state output element that has an OR function for at least two inputs. a first gate for selectively feeding back an output to one input of said tri-state output element; and said first gate for selectively outputting a signal provided to another input of said tri-state output element. a second gate that is operated exclusively with the gate, and the conversion of the first gate to the on state or off state at the rise or fall of the clock signal is the off state or on of the second gate. The output of the bit corresponding unit of the latch circuit section is wire-OR-combined with the bit output of the output data corresponding to the output data of the second data processing section. It is characterized by being A detailed explanation will be given below with reference to the drawings. Third
The figure shows the configuration of an embodiment of the latch circuit used in the present invention.
The figure shows the configuration of another embodiment of the latch circuit section used in the present invention.
FIG. 5 shows an embodiment of the present invention in which a latch circuit section is used in the output stage of a local storage, and FIG. 6 shows a time chart explaining its operation. In FIG. 3, 6 is a latch circuit, 7-1 is not provided, 7-n is a bit corresponding unit, 8-1 to 81n, 9-1 to 9-n is an AND circuit, and 10-1 is not provided. , and 101n each tried.
State output OR logic elements, 11 and 13 are respectively /
It represents a cut circuit.

A latch operation in one bit corresponding unit, for example 7-1, is performed as follows.

That is, '1} Now, the illustrated output control signal (OUTPUTC
ONTL) is applied, when the clock signal (CLOCK) rises to logic "1", AND circuits 8-1 are first turned off, and then AND circuits 9-1 are turned off.
is turned on.

'2) With AND circuit 9-1 turned on, input signal IB is supplied to tri-state output OR logic element 10-1, and output IY appears. At this time, the AND circuit 8-1 is kept in an off state. '3}
When the clock signal next falls to logic "0", AND circuit 8-1 is first turned on, and then AND circuit 9-1 is turned off.

'41 As a result, the output IY of the tri-state output off logic element 10-1 is input to the element 10-- through the AND circuit 8-1, and then the AND circuit 9-1 is turned off.

'51 From then on, the output of the tri-state output OR logic element 10 maintains the original output IY until the clock signal rises again.

'6} When the clock signal rises and then falls again, the input signal is newly latched through the above operations {1) to 5-.

In the latch circuit section 6 shown in FIG. 3, the latch operation is performed in each of the bit corresponding units 7-1 and 7-n as described above.

Each output terminal of the latch circuit section 6 is physically connected to, for example, each bit output terminal of the register 5 shown in FIG. 2 via another tri-state element, and is wired-OR coupled. FIG. 4 shows a modification of the latch circuit section 6 shown in FIG.
-1 L, 81 n, 9 1 none, 9 - n, 11, 1
2 and 13 correspond to FIG. 3, 14--14-n represent tri-state output NOR logic elements, and 15-1 and 15-n represent NOT circuits, respectively.

In the case shown in FIG. 4, only the tri-state output NOR logic element 14-i and the NOT circuit 15-i are used, and its operation is essentially the same as the case shown in FIG. 3. . FIG. 5 shows an embodiment of the present invention in which the latch circuit shown in FIG. 3 or 4 is used in the output stage of a local storage, and FIG. 6 shows a time chart explaining its operation. There is.

The symbols IA and IB in the figure together correspond to local storage according to the present invention, and the local storage is composed of independently accessible storage units IA and IB.

2 represents an arithmetic unit, and 5A and 5B correspond to the register 5 shown in FIG. 2, respectively.

6A and 6B together correspond to the latch circuit section according to the present invention, and the latch circuit section independently corresponds to the storage units IA and I.
It is composed of latch circuit units 6A and 6B that latch the output of B.

It should be noted that each latch circuit unit 6A and/or 6B may be considered to have the configuration shown in FIG. 3 or 4 above. 7A and 7B are the wired-or logic section and ADRS, respectively.
A and ADRSB are address information, WE is a write enable signal, CL-OCK is a clock signal shown in FIG. 3 or 4, and OTCA and OTCB are output control signals (OUTPUTCONTL shown in FIG. 3 or 4, respectively).
) represents a signal corresponding to

The memory units IA and IB are configured to be accessible independently, and as will be explained with reference to FIG.
The same data is stored at the same address location.

Now, let us consider a process in which the contents of address location ADRSX and address location ADRSY in local storages IA and IB are calculated and stored in address location ADRSX.

[7} In this case, as shown in the time chart of FIG. 6, a read access is made to the memory unit IA using the address ADRSY, and a read access is made to the memory unit IB using the address ADRSX.

(8} Then, the clock signal (CLOCK) given to the latch circuit units 6A and 6B is raised, and the data (ADRSY) read from the memory unit IA is latched by the latch circuit unit 6A and read from the memory unit IB. The data (ADRSX) is latched in the latch circuit unit 6B and is calculated by the calculation unit 2. Then, for example, in accordance with the timing when the clock signal (CLOCK) falls,
Access to storage unit IA is performed using address ADRSX.

00 At the timing when the next main clock is generated, the calculation result by the calculation unit 2 has been obtained, and the above calculation is stored in the address locations ADRSX of the storage units IA and IB in accordance with the next main clock. The result is stored.

(11) That is, the same content is stored at the same address location in the two storage units IA and IB.

(12) Also, the latch circuit unit 6A has a clock signal (C
The data (ADRSY) is held after the falling edge of LOCK until it rises again, and the latch circuit unit 6
Similarly, data (ADRSX) is held in B.

(13) Of course, if the contents of register SA or register 5B are used in the calculation, the wired-OR logic section 7
It is supplied to the arithmetic unit 2 via A and 7B.

The configuration shown in FIG. 5 has been increasingly used recently.

It has the same function as so-called 2-board RAM.
That is, the function of the two-boat RAM can be achieved by two storage units and two latch circuit units. A drawback of the circuit configuration shown in FIG. 5 is that, for example, when an operation using the register 5A is executed, the contents of the latch circuit section 6A are destroyed.

However, there is no problem if the contents of the storage unit IA are read from the storage unit IA and latched into the latch circuit unit 6A during a machine cycle when the contents of the storage unit IA are required, for example.
This method is common in vertical microinstruction control. In the above description of the illustration in FIG. 5, it was shown that the storage units IA and IB are used, but it goes without saying that the configuration shown in FIG. 3 or 4 may be used for the latch circuit section 6 in the configuration shown in FIG. 2. Needless to say, you can get it.

As described above, according to the present invention, a latch circuit capable of wired-OR coupling using tri-state output elements can be applied to a data processing device.

In the above description of the embodiment, it has been shown that the latch circuit section 6 is used as an output stage of a local storage, but it goes without saying that the latch circuit section 6 is not limited thereto and can be used, for example, as an output stage of an arithmetic unit.

Furthermore, although it is shown in FIG. 3 or 4 that an AND circuit is used for the first gate 8-i and the second gate 9-i as the latch circuit section 6, the present invention is not limited to this.

[Brief explanation of the drawing]

1 and 2 are explanatory diagrams for explaining the prerequisite problems of the present invention, FIGS. 3 and 4 respectively show an example configuration of a latch circuit used in the present invention, and FIG.・One embodiment of the present invention used in the output stage of storage, No. 6
The figure shows a time chart explaining its operation. In the figure, 1 is a local storage, IA and IB are storage units, 2 is an arithmetic unit, 5 is a second data processing section, 6 is a latch circuit section, 6A and 6B are latch circuit units, 7, 7A, 7B represents the wired-or logic section. Fig. 1 Fig. 2 Fig. 3 Fig. 4 Fig. 5 Fig. 6

Claims (1)

[Scope of Claims] 1. A first data processing unit having a function of calculating and/or holding given data, a latch circuit unit that latches output data from the data processing unit, and an output of the latch circuit unit. A second data processing section is provided which is coupled to an output from the first data processing section by wired-OR logic, and the latch output data obtained by latching the output data of the first data processing section by the latch circuit section and the second data processing section are provided. The output data corresponding to the output data of the data processing section of
In a data processing device having a latch circuit section that performs extraction by OR logic, the latch circuit section has an output controlled by an output control signal in each bit corresponding unit, and performs an OR function for at least two inputs. a first gate that selectively feeds back an output from the tri-state output element to one input of the tri-state output element and another input of the tri-state output element; The first gate selectively outputs the signal supplied to the clock signal and the second gate is operated exclusively, and the first gate is turned on or off at the rise or fall of the clock signal. The second gate is configured such that the conversion to the off state or the on state occurs earlier than the conversion to the off state or on state of the second gate,
A data processing device having a latch circuit section, wherein the output of the bit corresponding unit of the latch circuit section is wired-OR coupled with the bit output of the output data corresponding to the output data of the second data processing section. 2. Claim 1, wherein the first data processing device is constituted by a storage device that is accessed based on address information, and the latch circuit section latches read data from the storage device. A data processing device having the latch circuit section described above. The storage device is composed of a plurality of memory units that can be accessed independently, and the latch circuit section is composed of a plurality of latch circuit units that independently latch read data from each of the plurality of memory units. A data processing device having a latch circuit unit according to claim 2.