JPS55132123A - Rz-waveform output flip flop circuit - Google Patents

Rz-waveform output flip flop circuit

Info

Publication number
JPS55132123A
JPS55132123A JP3914379A JP3914379A JPS55132123A JP S55132123 A JPS55132123 A JP S55132123A JP 3914379 A JP3914379 A JP 3914379A JP 3914379 A JP3914379 A JP 3914379A JP S55132123 A JPS55132123 A JP S55132123A
Authority
JP
Japan
Prior art keywords
circuit
terminal
clock signal
input data
flip flop
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP3914379A
Other languages
Japanese (ja)
Inventor
Koichi Kobayashi
Hiroshi Fujimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP3914379A priority Critical patent/JPS55132123A/en
Publication of JPS55132123A publication Critical patent/JPS55132123A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03K—PULSE TECHNIQUE
    • H03K5/00—Manipulating of pulses not covered by one of the other main groups of this subclass
    • H03K5/22—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral
    • H03K5/24—Circuits having more than one input and one output for comparing pulses or pulse trains with each other according to input signal characteristics, e.g. slope, integral the characteristic being amplitude

Landscapes

  • Physics & Mathematics (AREA)
  • Nonlinear Science (AREA)

Abstract

PURPOSE:To simplify circuit constitution while reducing power consumption by providing two gate circuits and a reset priority FF circuit. CONSTITUTION:Gate circuit (e) and (f) and reset priority FF circuit (g) are provided. When the clock signal of terminal 2 is [0], the outputs of terminals 6 and 7 are [1] and [0], and circuits (e) and (g) are impassive and active states respectively. At this time, when the data signal of input 1 is [1], terminal 4 is [1] and when [0], terminal 4 is [0]; and since circuit (g) is impassive, terminal 3 is [0] without reference to the input data. Next, when the clock signal is [1], the opposite states to those mentioned above are set. Namely, terminal 3 is [1] only when input data is [1] and clock signal is also [1] the moment the clock signal changes from [0] to [1], so that this circuit will discriminates the input data momentarily at the point in time of the rise of the block so as to send the RZ waveform.
JP3914379A 1979-03-30 1979-03-30 Rz-waveform output flip flop circuit Pending JPS55132123A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP3914379A JPS55132123A (en) 1979-03-30 1979-03-30 Rz-waveform output flip flop circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3914379A JPS55132123A (en) 1979-03-30 1979-03-30 Rz-waveform output flip flop circuit

Publications (1)

Publication Number Publication Date
JPS55132123A true JPS55132123A (en) 1980-10-14

Family

ID=12544876

Family Applications (1)

Application Number Title Priority Date Filing Date
JP3914379A Pending JPS55132123A (en) 1979-03-30 1979-03-30 Rz-waveform output flip flop circuit

Country Status (1)

Country Link
JP (1) JPS55132123A (en)

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