JPS55134367A

JPS55134367A - Device for testing digital ic

Info

Publication number: JPS55134367A
Application number: JP4178579A
Authority: JP
Inventors: Sadaaki Tanaka
Original assignee: NEC Corp; Nippon Electric Co Ltd
Current assignee: NEC Corp
Priority date: 1979-04-06
Filing date: 1979-04-06
Publication date: 1980-10-20

Abstract

PURPOSE: To simplify the test operation of a digital IC and reduce the number of patterns in the IC by synchronizing the varying point of an expected pattern with either of standard or clock signals.

CONSTITUTION: A timing selector circuit 14 receives a standard signal T₀ from a timing generator 3 and a polyphase timing signal including a polyphase clock signal from an IC to be tested to select the leading or trailing edge of the timing signal at each of pins, and produces it to a latch circuit 12. Thus, the selector circuit selects the standard signal T₀ and the leading or trailing edge of the respective polyphase timing signals as a timing signal for latching the data from a memory 10. When the trailing edge of the timing signal used for a clock signal 16 is employed, for example, as the varying point of an expected pattern 20, the output 17 of the IC to be tested is synchronized with the trailing edge of the clock signal 16 and outputted with a delay Td₂.