JPS5462745A - Test equipment for logic circuit - Google Patents

Test equipment for logic circuit

Info

Publication number
JPS5462745A
JPS5462745A JP12938077A JP12938077A JPS5462745A JP S5462745 A JPS5462745 A JP S5462745A JP 12938077 A JP12938077 A JP 12938077A JP 12938077 A JP12938077 A JP 12938077A JP S5462745 A JPS5462745 A JP S5462745A
Authority
JP
Japan
Prior art keywords
circuit
logic circuit
signal group
output
synchronizing
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12938077A
Other languages
Japanese (ja)
Inventor
Mikiyuki Zaisho
Yoshihiro Kasuya
Teruhiko Yamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP12938077A priority Critical patent/JPS5462745A/en
Publication of JPS5462745A publication Critical patent/JPS5462745A/en
Pending legal-status Critical Current

Links

Landscapes

  • Test And Diagnosis Of Digital Computers (AREA)
  • Tests Of Electronic Circuits (AREA)

Abstract

PURPOSE: To enable a simple logic circuit to detect an undesirable pulse generated transiently with high reliability, by applying an input to a tested logic circuit after a reference logic circuit becomes stable.
CONSTITUTION: Synchronizing with clock pulse C, test input signal group I is set to data register 3 first and reference logic circuit 5 outputs signal group X1. Synchronizing with clock pulse C1 delayed by Δr, signal group I is set to data register 4 next, and tested logic circuit 6 outputs signal group X2. Quality decision circuit 7 decides the quality be comparing signal group X1 with X2. After data set signal C1 is inputted, output signal Z of circuit 7 becomes "1" in logic level when it is different from the output of circuit 5 after stabilized or when an undesirable transient pulse appears at the output of circuit 6, thereby discriminating circuit 6 as a defect.
COPYRIGHT: (C)1979,JPO&Japio
JP12938077A 1977-10-27 1977-10-27 Test equipment for logic circuit Pending JPS5462745A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12938077A JPS5462745A (en) 1977-10-27 1977-10-27 Test equipment for logic circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12938077A JPS5462745A (en) 1977-10-27 1977-10-27 Test equipment for logic circuit

Publications (1)

Publication Number Publication Date
JPS5462745A true JPS5462745A (en) 1979-05-21

Family

ID=15008140

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12938077A Pending JPS5462745A (en) 1977-10-27 1977-10-27 Test equipment for logic circuit

Country Status (1)

Country Link
JP (1) JPS5462745A (en)

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