JPS55137723A - Digital analogue converter - Google Patents

Digital analogue converter

Info

Publication number
JPS55137723A
JPS55137723A JP4623379A JP4623379A JPS55137723A JP S55137723 A JPS55137723 A JP S55137723A JP 4623379 A JP4623379 A JP 4623379A JP 4623379 A JP4623379 A JP 4623379A JP S55137723 A JPS55137723 A JP S55137723A
Authority
JP
Japan
Prior art keywords
bit
output
resistance
generated
ladder
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP4623379A
Other languages
Japanese (ja)
Inventor
Tadashi Azegami
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Yokogawa Electric Corp
Original Assignee
Hokushin Electric Works Ltd
Yokogawa Hokushin Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hokushin Electric Works Ltd, Yokogawa Hokushin Electric Corp filed Critical Hokushin Electric Works Ltd
Priority to JP4623379A priority Critical patent/JPS55137723A/en
Publication of JPS55137723A publication Critical patent/JPS55137723A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/66—Digital/analogue converters
    • H03M1/70—Automatic control for modifying converter range

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Analogue/Digital Conversion (AREA)

Abstract

PURPOSE:To prevent a void part from being generated in an analogue output quantity, by setting a weight for a special bit to a value below the double of the weight for the preceding bit in a D/A converter consisting of a binary counter and a weighting circuit. CONSTITUTION:The pulse train signal to be counted is supplied to up-count input 1a or down/count input 1b selectively through switch 11 from pulse generator 6. Output ai (i=0, 1..., 10) of binary counter 1 expresses 0 or 1 bit output, and the output voltage appears in case of 1. One end of resistance 2R is ladder-connected to bit outputs a1-a5 and a7-a10, and resistance R is ladder-connected to the other ends of bit outputs. Bit a6 is selected as a special bit and is connected to output 20 through resistance 32R. The ratio among resistances R, 2R and 32R is set to 1:2:32. Thus, the output is lowered for every 64 counts and rises hesitatingly, so that no void part may be generated in the analogue output. The resistance value connected to bit a 6 is so selected that no void over the allowable range of the analogue output may be generated.
JP4623379A 1979-04-16 1979-04-16 Digital analogue converter Pending JPS55137723A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4623379A JPS55137723A (en) 1979-04-16 1979-04-16 Digital analogue converter

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4623379A JPS55137723A (en) 1979-04-16 1979-04-16 Digital analogue converter

Publications (1)

Publication Number Publication Date
JPS55137723A true JPS55137723A (en) 1980-10-27

Family

ID=12741390

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4623379A Pending JPS55137723A (en) 1979-04-16 1979-04-16 Digital analogue converter

Country Status (1)

Country Link
JP (1) JPS55137723A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57101420A (en) * 1980-12-16 1982-06-24 Fujitsu Ltd Overflow detection system for analog-to-digital converter
JPS5876241U (en) * 1981-11-17 1983-05-23 カシオ計算機株式会社 Digital-to-analog converter output error compensation circuit
JPS59231714A (en) * 1983-06-13 1984-12-26 Matsushita Electric Ind Co Ltd Magnetic head

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS57101420A (en) * 1980-12-16 1982-06-24 Fujitsu Ltd Overflow detection system for analog-to-digital converter
JPS5876241U (en) * 1981-11-17 1983-05-23 カシオ計算機株式会社 Digital-to-analog converter output error compensation circuit
JPS59231714A (en) * 1983-06-13 1984-12-26 Matsushita Electric Ind Co Ltd Magnetic head

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