JPS55145358A - Method of forming metal wire pattern on semiconductor structure using etchinggresistant tungsten titanium layer - Google Patents

Method of forming metal wire pattern on semiconductor structure using etchinggresistant tungsten titanium layer

Info

Publication number
JPS55145358A
JPS55145358A JP5555780A JP5555780A JPS55145358A JP S55145358 A JPS55145358 A JP S55145358A JP 5555780 A JP5555780 A JP 5555780A JP 5555780 A JP5555780 A JP 5555780A JP S55145358 A JPS55145358 A JP S55145358A
Authority
JP
Japan
Prior art keywords
etchinggresistant
metal wire
semiconductor structure
titanium layer
forming metal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP5555780A
Other languages
English (en)
Other versions
JPH0371769B2 (ja
Inventor
Moorii Piaasu Jiyon
Iban Reeraa Uiriamu
Jiyosefu Radeigan Kenesu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fairchild Semiconductor Corp
Original Assignee
Fairchild Camera and Instrument Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fairchild Camera and Instrument Corp filed Critical Fairchild Camera and Instrument Corp
Publication of JPS55145358A publication Critical patent/JPS55145358A/ja
Publication of JPH0371769B2 publication Critical patent/JPH0371769B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
    • H10P50/268—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas of silicon-containing layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/26—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials
    • H10P50/264—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means
    • H10P50/266—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only
    • H10P50/267—Dry etching; Plasma etching; Reactive-ion etching of conductive or resistive materials by chemical means by vapour etching only using plasmas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/60—Wet etching
    • H10P50/66—Wet etching of conductive or resistive materials
    • H10P50/663—Wet etching of conductive or resistive materials by chemical means only
    • H10P50/667—Wet etching of conductive or resistive materials by chemical means only by liquid etching only
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/692—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their composition, e.g. multilayer masks or materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/694—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane characterised by their behaviour during the process, e.g. soluble masks or redeposited masks

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Drying Of Semiconductors (AREA)
  • Weting (AREA)
JP5555780A 1979-04-30 1980-04-28 Method of forming metal wire pattern on semiconductor structure using etchinggresistant tungsten titanium layer Granted JPS55145358A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/034,781 US4267012A (en) 1979-04-30 1979-04-30 Process for patterning metal connections on a semiconductor structure by using a tungsten-titanium etch resistant layer

Publications (2)

Publication Number Publication Date
JPS55145358A true JPS55145358A (en) 1980-11-12
JPH0371769B2 JPH0371769B2 (ja) 1991-11-14

Family

ID=21878557

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5555780A Granted JPS55145358A (en) 1979-04-30 1980-04-28 Method of forming metal wire pattern on semiconductor structure using etchinggresistant tungsten titanium layer

Country Status (2)

Country Link
US (1) US4267012A (ja)
JP (1) JPS55145358A (ja)

Families Citing this family (45)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4394678A (en) * 1979-09-19 1983-07-19 Motorola, Inc. Elevated edge-protected bonding pedestals for semiconductor devices
DE3005301C2 (de) * 1980-02-13 1985-11-21 Telefunken electronic GmbH, 7100 Heilbronn Varaktor- oder Mischerdiode
US4381215A (en) * 1980-05-27 1983-04-26 Burroughs Corporation Method of fabricating a misaligned, composite electrical contact on a semiconductor substrate
US4888297A (en) * 1982-09-20 1989-12-19 International Business Machines Corporation Process for making a contact structure including polysilicon and metal alloys
US4612257A (en) * 1983-05-02 1986-09-16 Signetics Corporation Electrical interconnection for semiconductor integrated circuits
US4517225A (en) * 1983-05-02 1985-05-14 Signetics Corporation Method for manufacturing an electrical interconnection by selective tungsten deposition
US4501061A (en) * 1983-05-31 1985-02-26 Advanced Micro Devices, Inc. Fluorine plasma oxidation of residual sulfur species
US4443295A (en) * 1983-06-13 1984-04-17 Fairchild Camera & Instrument Corp. Method of etching refractory metal film on semiconductor structures utilizing triethylamine and H2 O2
US4486946A (en) * 1983-07-12 1984-12-11 Control Data Corporation Method for using titanium-tungsten alloy as a barrier metal in silicon semiconductor processing
FR2561443B1 (fr) * 1984-03-19 1986-08-22 Commissariat Energie Atomique Procede pour interconnecter les zones actives et/ou les grilles d'un circuit integre cmos
US4672420A (en) * 1984-03-26 1987-06-09 Advanced Micro Devices, Inc. Integrated circuit structure having conductive, protective layer for multilayer metallization to permit reworking
US4845050A (en) * 1984-04-02 1989-07-04 General Electric Company Method of making mo/tiw or w/tiw ohmic contacts to silicon
US5111276A (en) * 1985-03-19 1992-05-05 National Semiconductor Corp. Thick bus metallization interconnect structure to reduce bus area
US4668335A (en) * 1985-08-30 1987-05-26 Advanced Micro Devices, Inc. Anti-corrosion treatment for patterning of metallic layers
EP0268426A3 (en) * 1986-11-17 1989-03-15 Linear Technology Corporation High speed junction field effect transistor for use in bipolar integrated circuits
USRE34821E (en) * 1986-11-17 1995-01-03 Linear Technology Corporation High speed junction field effect transistor for use in bipolar integrated circuits
NL8701032A (nl) * 1987-05-01 1988-12-01 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting met interconnecties die zowel boven een halfgeleidergebied als boven een daaraan grenzend isolatiegebied liggen.
US4787958A (en) * 1987-08-28 1988-11-29 Motorola Inc. Method of chemically etching TiW and/or TiWN
NL8800220A (nl) * 1988-01-29 1989-08-16 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting, waarbij een metalen geleiderspoor op een oppervlak van een halfgeleiderlichaam wordt gebracht.
US5266835A (en) * 1988-02-02 1993-11-30 National Semiconductor Corporation Semiconductor structure having a barrier layer disposed within openings of a dielectric layer
US5229311A (en) * 1989-03-22 1993-07-20 Intel Corporation Method of reducing hot-electron degradation in semiconductor devices
US4874713A (en) * 1989-05-01 1989-10-17 Ncr Corporation Method of making asymmetrically optimized CMOS field effect transistors
KR920005701B1 (ko) * 1989-07-20 1992-07-13 현대전자산업 주식회사 반도체 집적회로 내의 소자 연결용 금속배선층 및 그 제조방법
JP2509713B2 (ja) * 1989-10-18 1996-06-26 シャープ株式会社 炭化珪素半導体装置およびその製造方法
US4976809A (en) * 1989-12-18 1990-12-11 North American Philips Corp, Signetics Division Method of forming an aluminum conductor with highly oriented grain structure
US5141897A (en) * 1990-03-23 1992-08-25 At&T Bell Laboratories Method of making integrated circuit interconnection
US5225040A (en) * 1990-04-16 1993-07-06 Raytheon Company Process for patterning metal connections in small-geometry semiconductor structures
US5296407A (en) * 1990-08-30 1994-03-22 Seiko Epson Corporation Method of manufacturing a contact structure for integrated circuits
US5192703A (en) * 1991-10-31 1993-03-09 Micron Technology, Inc. Method of making tungsten contact core stack capacitor
US5227325A (en) * 1992-04-02 1993-07-13 Micron Technology, Incl Method of forming a capacitor
US5376585A (en) * 1992-09-25 1994-12-27 Texas Instruments Incorporated Method for forming titanium tungsten local interconnect for integrated circuits
US5556507A (en) * 1994-03-03 1996-09-17 Silicon Systems, Inc. Multifunctional contactless interconnect technology
JPH08162425A (ja) 1994-12-06 1996-06-21 Mitsubishi Electric Corp 半導体集積回路装置の製造方法および製造装置
US5952244A (en) * 1996-02-15 1999-09-14 Lam Research Corporation Methods for reducing etch rate loading while etching through a titanium nitride anti-reflective layer and an aluminum-based metallization layer
US6004884A (en) * 1996-02-15 1999-12-21 Lam Research Corporation Methods and apparatus for etching semiconductor wafers
US5846443A (en) * 1996-07-09 1998-12-08 Lam Research Corporation Methods and apparatus for etching semiconductor wafers and layers thereof
US5911887A (en) * 1996-07-19 1999-06-15 Cypress Semiconductor Corporation Method of etching a bond pad
US5883007A (en) * 1996-12-20 1999-03-16 Lam Research Corporation Methods and apparatuses for improving photoresist selectivity and reducing etch rate loading
US5980768A (en) * 1997-03-07 1999-11-09 Lam Research Corp. Methods and apparatus for removing photoresist mask defects in a plasma reactor
US6087266A (en) * 1997-06-27 2000-07-11 Lam Research Corporation Methods and apparatus for improving microloading while etching a substrate
US6090304A (en) * 1997-08-28 2000-07-18 Lam Research Corporation Methods for selective plasma etch
US6187667B1 (en) 1998-06-17 2001-02-13 Cypress Semiconductor Corp. Method of forming metal layer(s) and/or antireflective coating layer(s) on an integrated circuit
US20050032351A1 (en) * 1998-12-21 2005-02-10 Mou-Shiung Lin Chip structure and process for forming the same
US6191046B1 (en) 1999-03-11 2001-02-20 Advanced Micro Devices, Inc. Deposition of an oxide layer to facilitate photoresist rework on polygate layer
US6798073B2 (en) 2001-12-13 2004-09-28 Megic Corporation Chip structure and process for forming the same

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5254378A (en) * 1975-10-29 1977-05-02 Fujitsu Ltd Production of semiconductor device
JPS5374392A (en) * 1976-12-15 1978-07-01 Hitachi Ltd Multi-layer coat formation method
JPS5494196A (en) * 1977-12-30 1979-07-25 Ibm Metallic layer removing method

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3480412A (en) * 1968-09-03 1969-11-25 Fairchild Camera Instr Co Method of fabrication of solder reflow interconnections for face down bonding of semiconductor devices
US3615956A (en) * 1969-03-27 1971-10-26 Signetics Corp Gas plasma vapor etching process
US3881971A (en) * 1972-11-29 1975-05-06 Ibm Method for fabricating aluminum interconnection metallurgy system for silicon devices
US3881884A (en) * 1973-10-12 1975-05-06 Ibm Method for the formation of corrosion resistant electronic interconnections
US3900944A (en) * 1973-12-19 1975-08-26 Texas Instruments Inc Method of contacting and connecting semiconductor devices in integrated circuits
GB1499857A (en) * 1975-09-18 1978-02-01 Standard Telephones Cables Ltd Glow discharge etching
US4069096A (en) * 1975-11-03 1978-01-17 Texas Instruments Incorporated Silicon etching process
US4021270A (en) * 1976-06-28 1977-05-03 Motorola, Inc. Double master mask process for integrated circuit manufacture
US4057460A (en) * 1976-11-22 1977-11-08 Data General Corporation Plasma etching process
US4141022A (en) * 1977-09-12 1979-02-20 Signetics Corporation Refractory metal contacts for IGFETS
US4172004A (en) * 1977-10-20 1979-10-23 International Business Machines Corporation Method for forming dense dry etched multi-level metallurgy with non-overlapped vias

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5254378A (en) * 1975-10-29 1977-05-02 Fujitsu Ltd Production of semiconductor device
JPS5374392A (en) * 1976-12-15 1978-07-01 Hitachi Ltd Multi-layer coat formation method
JPS5494196A (en) * 1977-12-30 1979-07-25 Ibm Metallic layer removing method

Also Published As

Publication number Publication date
US4267012A (en) 1981-05-12
JPH0371769B2 (ja) 1991-11-14

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