JPS55147724A - Data input system - Google Patents

Data input system

Info

Publication number
JPS55147724A
JPS55147724A JP5521879A JP5521879A JPS55147724A JP S55147724 A JPS55147724 A JP S55147724A JP 5521879 A JP5521879 A JP 5521879A JP 5521879 A JP5521879 A JP 5521879A JP S55147724 A JPS55147724 A JP S55147724A
Authority
JP
Japan
Prior art keywords
data
fed
signal
circuits
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5521879A
Other languages
Japanese (ja)
Inventor
Noboru Murayama
Hirosada Yamada
Kaoru Konno
Seiji Ishimitsu
Yoshio Yagi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Ricoh Co Ltd
Original Assignee
Ricoh Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Ricoh Co Ltd filed Critical Ricoh Co Ltd
Priority to JP5521879A priority Critical patent/JPS55147724A/en
Publication of JPS55147724A publication Critical patent/JPS55147724A/en
Pending legal-status Critical Current

Links

Landscapes

  • Input From Keyboards Or The Like (AREA)
  • Calculators And Similar Devices (AREA)

Abstract

PURPOSE: To enable to prevent misinput through the discrimination of data distinction, by the input of a plurality of keyings to one data and distinguishing the order of sound with the input, in inputting the data by use of the keyboard.
CONSTITUTION: The data from the keyboard 2 is received at the reception circuit 8 and fed to the memory unit 7. On the other hand, the data sampling DS signal (b) is received at the reception circuit 10 and fed to CPU1 via the memory unit 7, counter 11, and interface. Further, the counter 11 is operated with the instruction of CPU11, the signal (b) is converted into a given signal, and the signals (c) and (d) are respectively fed to the AND circuits 15 and 16. When the instruction to drive the speaker from the CPU1 to the monostable mltivibrators 12 and 13 is output, the output signals (e) and (f) are fed to the circuits 15 and 16 from the nomostable multivibrators 12 and 13. Further, the speaker driving signal (a) from the oscillator 14 is input to the circuits 15 and 16 to distinct the data and prevent the misinput.
COPYRIGHT: (C)1980,JPO&Japio
JP5521879A 1979-05-08 1979-05-08 Data input system Pending JPS55147724A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5521879A JPS55147724A (en) 1979-05-08 1979-05-08 Data input system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5521879A JPS55147724A (en) 1979-05-08 1979-05-08 Data input system

Publications (1)

Publication Number Publication Date
JPS55147724A true JPS55147724A (en) 1980-11-17

Family

ID=12992468

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5521879A Pending JPS55147724A (en) 1979-05-08 1979-05-08 Data input system

Country Status (1)

Country Link
JP (1) JPS55147724A (en)

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