JPS55150257A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS55150257A
JPS55150257A JP5712279A JP5712279A JPS55150257A JP S55150257 A JPS55150257 A JP S55150257A JP 5712279 A JP5712279 A JP 5712279A JP 5712279 A JP5712279 A JP 5712279A JP S55150257 A JPS55150257 A JP S55150257A
Authority
JP
Japan
Prior art keywords
melting point
decomposition temperature
substrate
package
resin
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP5712279A
Other languages
Japanese (ja)
Inventor
Kanji Otsuka
Tamotsu Usami
Katsumi Ogiue
Kazumichi Mitsusada
Masao Sekihashi
Michiaki Furukawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Ltd
Original Assignee
Hitachi Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd filed Critical Hitachi Ltd
Priority to JP5712279A priority Critical patent/JPS55150257A/en
Publication of JPS55150257A publication Critical patent/JPS55150257A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
    • H10W76/10—Containers or parts thereof
    • H10W76/12—Containers or parts thereof characterised by their shape
    • H10W76/15—Containers comprising an insulating or insulated base
    • H10W76/157—Containers comprising an insulating or insulated base having interconnections parallel to the insulating or insulated base
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/015—Manufacture or treatment of bond wires
    • H10W72/01515—Forming coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Abstract

PURPOSE:To obtain highly reliable ceramic package by employing substantially the same as or lower melting point than the decomposition temperature of the protective film of organic material formed on the surface of a semiconductor chip partly on the seal of the chip. CONSTITUTION:A lead wire 12 is adhered via a low melting point glass 11 on the upper surface of an alumina ceramic substrate 10, and a semiconductor chip 14 is bonded at 13 to the recess thereon. After forming a connecting wire 15 thereon, a polyimide resin 16 is coated thereon, a cap 17 of the same material as the substrate 10 is superimposed on the substrate 10, and is sealed with low melting point glass 18. The galss 18 has lower melting point as the decomposition temperature of the polyimide resin 16 or substantially equal melting point to the decomposition temperature of the resin 16. According to this configuration, the cost thereof is reduced lower than the laminated package to prevent the adverse affect of alpha rays irradiated from the package by the resin layer. Further, the semiconductor and the seal are not adversely affected due to the presence of the gas caused by the decomposition of the organic material 16.
JP5712279A 1979-05-11 1979-05-11 Semiconductor device Pending JPS55150257A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP5712279A JPS55150257A (en) 1979-05-11 1979-05-11 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP5712279A JPS55150257A (en) 1979-05-11 1979-05-11 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS55150257A true JPS55150257A (en) 1980-11-22

Family

ID=13046741

Family Applications (1)

Application Number Title Priority Date Filing Date
JP5712279A Pending JPS55150257A (en) 1979-05-11 1979-05-11 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS55150257A (en)

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