JPS55165012A - Amplifier - Google Patents
AmplifierInfo
- Publication number
- JPS55165012A JPS55165012A JP7217679A JP7217679A JPS55165012A JP S55165012 A JPS55165012 A JP S55165012A JP 7217679 A JP7217679 A JP 7217679A JP 7217679 A JP7217679 A JP 7217679A JP S55165012 A JPS55165012 A JP S55165012A
- Authority
- JP
- Japan
- Prior art keywords
- signal
- amplifier
- circuit
- voltage
- fed
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03G—CONTROL OF AMPLIFICATION
- H03G3/00—Gain control in amplifiers or frequency changers
- H03G3/20—Automatic control
- H03G3/30—Automatic control in amplifiers having semiconductor devices
- H03G3/34—Muting amplifier when no signal is present
- H03G3/348—Muting in response to a mechanical action or to power supply variations, e.g. during tuning; Click removal circuits
Landscapes
- Control Of Amplification And Gain Control (AREA)
Abstract
PURPOSE:To prevent the production of transient oscillation in the amplifier and that of interferring voltage to external circuits by clamping the output voltage of amplifier to a given voltage during the period immediately after and before the power down. CONSTITUTION:The reception signal Vin is input to the terminal 11 and fed to the amplifier 12, and no signal Vin is for a certain period. This no-input period is detected at the monitor circuit and the power down command signal PD is fed to the terminal 24. The control circuit 23 of the interface 21 receives the signal PD, the switch switching control signal PS is fed to the switch 22 for closing, and the output of the amplifier 12 is clamped to a given voltage (ground). Next, the circuit 23 delivers the power down command signal PD to the terminal 13 with somewhat delay. When the signal PD is released, the circuit 23 first releases the signal PD, and the switch 22 is OFF with a slight delay than it. Accordingly, the output of the amplifier 12 at the transient period of application of the signal PD and release is clamped at the ground voltage and the interference to the external circuit C is prevented.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7217679A JPS55165012A (en) | 1979-06-11 | 1979-06-11 | Amplifier |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7217679A JPS55165012A (en) | 1979-06-11 | 1979-06-11 | Amplifier |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS55165012A true JPS55165012A (en) | 1980-12-23 |
| JPS6226205B2 JPS6226205B2 (en) | 1987-06-08 |
Family
ID=13481647
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7217679A Granted JPS55165012A (en) | 1979-06-11 | 1979-06-11 | Amplifier |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS55165012A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59229921A (en) * | 1983-05-23 | 1984-12-24 | Rohm Co Ltd | Switch circuit |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5490954A (en) * | 1977-12-28 | 1979-07-19 | Matsushita Electric Ind Co Ltd | Amplifier |
-
1979
- 1979-06-11 JP JP7217679A patent/JPS55165012A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5490954A (en) * | 1977-12-28 | 1979-07-19 | Matsushita Electric Ind Co Ltd | Amplifier |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS59229921A (en) * | 1983-05-23 | 1984-12-24 | Rohm Co Ltd | Switch circuit |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6226205B2 (en) | 1987-06-08 |
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