JPS5518005A - Mos-type dynamic memory - Google Patents
Mos-type dynamic memoryInfo
- Publication number
- JPS5518005A JPS5518005A JP8997578A JP8997578A JPS5518005A JP S5518005 A JPS5518005 A JP S5518005A JP 8997578 A JP8997578 A JP 8997578A JP 8997578 A JP8997578 A JP 8997578A JP S5518005 A JPS5518005 A JP S5518005A
- Authority
- JP
- Japan
- Prior art keywords
- substrate
- region
- mos
- dynamic memory
- constitution
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000000758 substrate Substances 0.000 abstract 4
- 239000000969 carrier Substances 0.000 abstract 1
- 238000005468 ion implantation Methods 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B12/00—Dynamic random access memory [DRAM] devices
- H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
Landscapes
- Semiconductor Memories (AREA)
Abstract
PURPOSE:To reduce noises and to make the size small by separating a memory circuit and other elements by providing an insulating layer to the depth of 1mum or more from the surface of a substrate. CONSTITUTION:Regions 1 and 2 are formed on a same substrate 9. A memory cell 3 is formed on the region 1; and a gate 4, a source 5, and a drain 6 are formed on the region 2. An insulating layer 7 is formed by ion implantation and the like so that it reaches the point sufficiently deep from the surface, thereby minority carriers which are generated in the substrate 9 and are capable of moving in the substrate 9 are prevented from moving into the region 1. In this constitution, noises are eliminated, holding characteristics can be enhanced accordingly, and the size can be reduced.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8997578A JPS5518005A (en) | 1978-07-25 | 1978-07-25 | Mos-type dynamic memory |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8997578A JPS5518005A (en) | 1978-07-25 | 1978-07-25 | Mos-type dynamic memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS5518005A true JPS5518005A (en) | 1980-02-07 |
Family
ID=13985669
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8997578A Pending JPS5518005A (en) | 1978-07-25 | 1978-07-25 | Mos-type dynamic memory |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5518005A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56135959A (en) * | 1980-03-28 | 1981-10-23 | Nec Corp | Semiconductor ic device |
| JPS58106858A (en) * | 1981-12-18 | 1983-06-25 | Nec Corp | Semiconductor integrated circuit |
| JPS6074564A (en) * | 1983-09-30 | 1985-04-26 | Toshiba Corp | Semiconductor memory device |
| JPH02354A (en) * | 1989-02-08 | 1990-01-05 | Hitachi Ltd | Large scale semiconductor memory and its manufacture |
-
1978
- 1978-07-25 JP JP8997578A patent/JPS5518005A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS56135959A (en) * | 1980-03-28 | 1981-10-23 | Nec Corp | Semiconductor ic device |
| JPS58106858A (en) * | 1981-12-18 | 1983-06-25 | Nec Corp | Semiconductor integrated circuit |
| JPS6074564A (en) * | 1983-09-30 | 1985-04-26 | Toshiba Corp | Semiconductor memory device |
| JPH02354A (en) * | 1989-02-08 | 1990-01-05 | Hitachi Ltd | Large scale semiconductor memory and its manufacture |
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