JPS5518921A - Process display of measured value - Google Patents

Process display of measured value

Info

Publication number
JPS5518921A
JPS5518921A JP9120178A JP9120178A JPS5518921A JP S5518921 A JPS5518921 A JP S5518921A JP 9120178 A JP9120178 A JP 9120178A JP 9120178 A JP9120178 A JP 9120178A JP S5518921 A JPS5518921 A JP S5518921A
Authority
JP
Japan
Prior art keywords
signals
minimum
maximum
measured
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9120178A
Other languages
Japanese (ja)
Inventor
Shinobu Sagisawa
Shigeo Oshima
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fuji Electric Co Ltd
Original Assignee
Fuji Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fuji Electric Co Ltd filed Critical Fuji Electric Co Ltd
Priority to JP9120178A priority Critical patent/JPS5518921A/en
Publication of JPS5518921A publication Critical patent/JPS5518921A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To simply test workings without any mistake by processing and recording the maximum and minimum of the measured values of several positions as digital signals.
CONSTITUTION: If the measured value of a single portion is fed as an analog signal from a measuring device 1 to a digitally converting circuit, the measured quantities as the output signals from the circuit 2 are fed to maximum and minimum comparators 3 and 4 so that they are written as the maximum and minimum memories in memories 5 and 6 and displayed in display devices 7 and 8. Then, the measured signals of the circuit 2 are eliminated through a reset circuit 9. When subsequent signals are given, the circuits 3 and 4 compare them with the stored values of the devices 5 and 6 to renew the signals to the stored values if they are higher or smaller than the latter. On the other hand, an output buffer 9 for receiving the measured signal upon each trial and memory output buffers 10 and 11 of the maximum and minimum are supplied with an output command so that the respective data are recorded in a printer or the like. Thus, the tests without any mistake can be easily performed.
COPYRIGHT: (C)1980,JPO&Japio
JP9120178A 1978-07-26 1978-07-26 Process display of measured value Pending JPS5518921A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9120178A JPS5518921A (en) 1978-07-26 1978-07-26 Process display of measured value

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9120178A JPS5518921A (en) 1978-07-26 1978-07-26 Process display of measured value

Publications (1)

Publication Number Publication Date
JPS5518921A true JPS5518921A (en) 1980-02-09

Family

ID=14019813

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9120178A Pending JPS5518921A (en) 1978-07-26 1978-07-26 Process display of measured value

Country Status (1)

Country Link
JP (1) JPS5518921A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62173066U (en) * 1986-04-23 1987-11-04

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5265463A (en) * 1975-11-27 1977-05-30 Casio Comput Co Ltd Digital meter

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5265463A (en) * 1975-11-27 1977-05-30 Casio Comput Co Ltd Digital meter

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62173066U (en) * 1986-04-23 1987-11-04

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