JPS55110331A - Process input-output unit - Google Patents

Process input-output unit

Info

Publication number
JPS55110331A
JPS55110331A JP1749579A JP1749579A JPS55110331A JP S55110331 A JPS55110331 A JP S55110331A JP 1749579 A JP1749579 A JP 1749579A JP 1749579 A JP1749579 A JP 1749579A JP S55110331 A JPS55110331 A JP S55110331A
Authority
JP
Japan
Prior art keywords
memory unit
signal
address
relay
selective
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1749579A
Other languages
Japanese (ja)
Inventor
Katsumi Murata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP1749579A priority Critical patent/JPS55110331A/en
Publication of JPS55110331A publication Critical patent/JPS55110331A/en
Pending legal-status Critical Current

Links

Landscapes

  • Feedback Control In General (AREA)
  • Control By Computers (AREA)

Abstract

PURPOSE: To make it possible to read an output value by a computer and also to simulate an external signal by a program by providing a memory unit, controller, etc., and using them for both input and output.
CONSTITUTION: The address of memory unit 23 corresponding to lamp 10 as address signal 26, a write indication as selective signal 27 and data set up for line 25 to turn lamp 25 ON are sent to memory unit 2 by computer 21. When selective signals 28 and 29 output output signals previously, lamp 10 can come on since controller 24 has outputted the contents of memory unit 23 to a process. When input is selected by selective signals 28 and 29, controller 24 writes the state of relay 11 at a corresponding address of memory unit 23. Therefore, the content of memory unit 23 varies with the variation of the contact of relay 11. Further, a read signal is outputted as selective signal 27 from the computer and the contact address of relay 11 is assigned as address signal 26, so that the current state of relay 11 can be judged.
COPYRIGHT: (C)1980,JPO&Japio
JP1749579A 1979-02-16 1979-02-16 Process input-output unit Pending JPS55110331A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1749579A JPS55110331A (en) 1979-02-16 1979-02-16 Process input-output unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1749579A JPS55110331A (en) 1979-02-16 1979-02-16 Process input-output unit

Publications (1)

Publication Number Publication Date
JPS55110331A true JPS55110331A (en) 1980-08-25

Family

ID=11945573

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1749579A Pending JPS55110331A (en) 1979-02-16 1979-02-16 Process input-output unit

Country Status (1)

Country Link
JP (1) JPS55110331A (en)

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