JPS5526666A - Insulated gate type semiconductor device - Google Patents

Insulated gate type semiconductor device

Info

Publication number
JPS5526666A
JPS5526666A JP9970178A JP9970178A JPS5526666A JP S5526666 A JPS5526666 A JP S5526666A JP 9970178 A JP9970178 A JP 9970178A JP 9970178 A JP9970178 A JP 9970178A JP S5526666 A JPS5526666 A JP S5526666A
Authority
JP
Japan
Prior art keywords
region
type
depression
substrate
mode transistor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9970178A
Other languages
Japanese (ja)
Inventor
Toshio Wada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP9970178A priority Critical patent/JPS5526666A/en
Publication of JPS5526666A publication Critical patent/JPS5526666A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/84—Combinations of enhancement-mode IGFETs and depletion-mode IGFETs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/83125—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] the IGFETs characterised by having shared source or drain regions

Landscapes

  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To materialize a speed-up of a device by providing an additional region in a depression mode transistor in mounting on a single substrate the depression and enhancement mode transistors. CONSTITUTION:An N<+>-type source region 4 and drain region 5 are provided in a P<->-type Si substrate 1, and a P<+>-type invasion region 6 is provided in the region 4 in opposition to the region 5. Subsequently, a multi-crystal Si gate electrode 3 is formed through a gate SiO2 film 2 on the substrate 1 disposed between the regions 4 and 5, to make up an enhancement mode transistor EMOST. Furthermore, utilizing commonly the region 5 for the source region, a depression mode transistor DMOST including a N<+>-type drain region 9, P<+>-type invasion region 10, gate insulated film 7 and gate electrode 8 is formed in contact with the EMOST. According to such a construction, a shallow N-type region 11 is additionally provided by an ion implanting between the regions 5 and 9 to materialize a speed-up of the DMOST used for a load element.
JP9970178A 1978-08-15 1978-08-15 Insulated gate type semiconductor device Pending JPS5526666A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9970178A JPS5526666A (en) 1978-08-15 1978-08-15 Insulated gate type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9970178A JPS5526666A (en) 1978-08-15 1978-08-15 Insulated gate type semiconductor device

Publications (1)

Publication Number Publication Date
JPS5526666A true JPS5526666A (en) 1980-02-26

Family

ID=14254350

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9970178A Pending JPS5526666A (en) 1978-08-15 1978-08-15 Insulated gate type semiconductor device

Country Status (1)

Country Link
JP (1) JPS5526666A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4680605A (en) * 1984-03-12 1987-07-14 Xerox Corporation High voltage depletion mode transistor with serpentine current path
US4906588A (en) * 1988-06-23 1990-03-06 Dallas Semiconductor Corporation Enclosed buried channel transistor
US4943537A (en) * 1988-06-23 1990-07-24 Dallas Semiconductor Corporation CMOS integrated circuit with reduced susceptibility to PMOS punchthrough
US5122474A (en) * 1988-06-23 1992-06-16 Dallas Semiconductor Corporation Method of fabricating a CMOS IC with reduced susceptibility to PMOS punchthrough
EP2065939A3 (en) * 2007-11-28 2009-10-21 Nanker(Guang Zhou)Semiconductor Manufacturing Corp Constant current source device and method for manufacturing the same

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4680605A (en) * 1984-03-12 1987-07-14 Xerox Corporation High voltage depletion mode transistor with serpentine current path
US4906588A (en) * 1988-06-23 1990-03-06 Dallas Semiconductor Corporation Enclosed buried channel transistor
US4943537A (en) * 1988-06-23 1990-07-24 Dallas Semiconductor Corporation CMOS integrated circuit with reduced susceptibility to PMOS punchthrough
US5122474A (en) * 1988-06-23 1992-06-16 Dallas Semiconductor Corporation Method of fabricating a CMOS IC with reduced susceptibility to PMOS punchthrough
US5688722A (en) * 1988-06-23 1997-11-18 Dallas Semiconductor Corporation CMOS integrated circuit with reduced susceptibility to PMOS punchthrough
EP2065939A3 (en) * 2007-11-28 2009-10-21 Nanker(Guang Zhou)Semiconductor Manufacturing Corp Constant current source device and method for manufacturing the same

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