JPS5528103A - Control method for peripheral unit - Google Patents

Control method for peripheral unit

Info

Publication number
JPS5528103A
JPS5528103A JP9863078A JP9863078A JPS5528103A JP S5528103 A JPS5528103 A JP S5528103A JP 9863078 A JP9863078 A JP 9863078A JP 9863078 A JP9863078 A JP 9863078A JP S5528103 A JPS5528103 A JP S5528103A
Authority
JP
Japan
Prior art keywords
power supply
peripheral unit
voltage
level
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9863078A
Other languages
Japanese (ja)
Inventor
Yukio Shimizu
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP9863078A priority Critical patent/JPS5528103A/en
Publication of JPS5528103A publication Critical patent/JPS5528103A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To control the input of error signal to computer, by providing a simple circuit at the computer side without requiring special application and interruption sequence to the power supply of peripheral unit.
CONSTITUTION: The error signals 8 and 9 are produced at a voltage less than the point in which the leading curve from the power supply ON(a) of the peripheral unit and the trailing curve from the power supply OFF(b) intersect with a given level A. Thus, the power supply voltage 2 (+5V) of the peripheral unit 1 is connected to one input of the comparator 6 via the cable 4, and the reference voltage generator (voltage at the level A) is connected to another input. When the power supply voltage is greater than the voltage at the level A, the comparator produces output of 1. The said output gates the signal on the signal cable of the peripheral unit to block the delivery of error signals produced at On or OFF of the power supply of the peripheral unit.
COPYRIGHT: (C)1980,JPO&Japio
JP9863078A 1978-08-15 1978-08-15 Control method for peripheral unit Pending JPS5528103A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9863078A JPS5528103A (en) 1978-08-15 1978-08-15 Control method for peripheral unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9863078A JPS5528103A (en) 1978-08-15 1978-08-15 Control method for peripheral unit

Publications (1)

Publication Number Publication Date
JPS5528103A true JPS5528103A (en) 1980-02-28

Family

ID=14224826

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9863078A Pending JPS5528103A (en) 1978-08-15 1978-08-15 Control method for peripheral unit

Country Status (1)

Country Link
JP (1) JPS5528103A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6452051U (en) * 1987-09-18 1989-03-30

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6452051U (en) * 1987-09-18 1989-03-30

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